Processor register error correction management
AssigneeInternational Business Machines Corporation
InventorsPradip Bose, Chen-Yong Cher, Meeta S. Gupta
Life of this patent
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Abstract
Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
Claims23
A method of processor register protection management, the method comprising:
- determining a sensitive logical register for executable code generated by a compiler;
- generating an error-correction table identifying the sensitive logical register;
- and
- storing the error-correction table in a memory accessible by a processor, wherein the processor is configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
A system for processor register protection management, the system comprising:
- a memory storing an error-correction table identifying a sensitive logical register for executable code generated by a compiler;
- and
- a processor having a plurality of registers, the processor configured to access the error-correction table in the memory and generate a duplicate register for the sensitive logical register identified by the error-correction table.
A method of processor register protection management, the method comprising:
- determining a floating point logical register for executable code generated by a compiler, the floating point logical register configured to store a floating point including a signage bit, a plurality of exponent bits, and a plurality of fraction bits, the plurality of fraction bits including a higher order bit and a lower order bit;
- generating a plurality of parity bits for the floating point logical register, the plurality of parity bits corresponding to the signage bit, the plurality of exponent bits, and the higher order bit.
A computer program product for processor register protection management, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:
- determining a sensitive logical register for executable code generated by a compiler;
- generating an error-correction table identifying the sensitive logical register;
- and
- storing the error-correction table in a memory accessible by a processor, wherein the processor is configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
Dependencies are inferred from the claim text.