System-on-chip verification

Abstract

Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals. During the hardware verification process, the AIC configures at least one of the communication protocols to enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a register-transfer level model is used for a least one of the plurality of peripherals. The AIC may further configure at least one of the communication protocols to enforce one or more constraints on the transactions to achieve increased hardware verification coverage.

Dependencies are inferred from the claim text.