Compile method and compiler apparatus
AssigneeFujitsu Limited
InventorsMasakazu UENO, Masahiro DOTEGUCHI
Life of this patent
Estimating the term…
Abstract
A compiler apparatus copies a branch instruction included in first code to produce a plurality of branch instructions. The compiler apparatus generates a control instruction to cause different threads running on a processor, which is able to execute a plurality of threads that share storage space for storing information to be used for branch prediction, to execute different ones of the plurality of branch instructions. The compiler apparatus generates second code including the plurality of branch instructions and the control instruction.
Claims6
A non-transitory computer-readable storage medium storing a computer program, the computer program causing a computer to perform a process comprising:
- copying a branch instruction included in first code to produce a plurality of branch instructions;
- generating a control instruction to cause different threads running on a processor to execute different branch instructions of the plurality of branch instructions, the processor being able to execute a plurality of threads that share storage space for storing information to be used for branch prediction;
- and
- generating second code including the plurality of branch instructions and the control instruction.
A compile method, comprising:
- copying, by a processor, a branch instruction included in first code to produce a plurality of branch instructions;
- generating, by the processor, a control instruction to cause different threads running on another processor to execute different branch instructions of the plurality of branch instructions, said another processor being able to execute a plurality of threads that share storage space for storing information to be used for branch prediction;
- and
- generating, by the processor, second code including the plurality of branch instructions and the control instruction.
A compiler apparatus comprising:
- a memory configured to store first code including a branch instruction;
- and
- a processor configured to perform a process including:
- copying the branch instruction included in the first code to produce a plurality of branch instructions;
- generating a control instruction to cause different threads running on another processor to execute different branch instructions of the plurality of branch instructions, said another processor being able to execute a plurality of threads that share storage space for storing information to be used for branch prediction;
- and
- generating second code including the plurality of branch instructions and the control instruction.
Dependencies are inferred from the claim text.