Arithmetic circuit and control method for arithmetic circuit

An arithmetic circuit comprising:

• first to N-th, N being an integer equal to or larger than three, element circuits respectively including:
• input circuits configured to input first operand data and second operand data;
• and
• element data selectors configured to select operand data of any of element circuits on the basis of a request element signal;
• and
• a data bus configured to supply the operand data input by the element circuits from the input circuits of the element circuits to the element data selectors of the element circuits, wherein
• when a control signal is in a first state, the element data selectors in the first to N-th element circuits respectively select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data,
• the arithmetic circuit further comprises a valid bit adder configured to add up, when the control signal is in a third state, valid bits included in the second operand data input by the first to N-th element circuits, and
• the first to N-th element circuits respectively include sum selectors configured to output, when the control signal is in a third state, a sum output by the valid bit adder instead of outputs of the element data selector.

An arithmetic circuit comprising:

• first to N-th, N being an integer equal to or larger than three, element circuits respectively including:
• input circuits configured to input first operand data and second operand data;
• element data selectors configured to select operand data of any of element circuits on the basis of a request element signal;
• and
• mask selectors configured to select outputs of the element data selectors or all-zero data;
• and
• a data bus configured to supply the operand data input by the element circuits from the input circuits of the element circuits to the element data selectors of the element circuits, wherein
• when a control signal is in a first state, the element data selectors in the first to N-th element circuits respectively select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data,
• when the control signal is in the first state, the mask selectors select outputs of the element data selectors,
• the arithmetic circuit further comprises a compress decoder configured to generate, when the control signal is in a fourth state, on the basis of valid bits included in the second operand data input by the first to N-th element circuits, a compress decode signal including a mask signal and an element data selection signal for each of the first to N-th element circuits, and
• the first to N-th element circuits respectively include:
• first compress selectors configured to select, when the control signal is in the fourth state, the element data selection signal, instead of the request element signal;
• and
• second compress selectors configured to output the mask signal to the mask selectors and cause the mask selectors to select the all-zero data.

An arithmetic circuit comprising:

• first to N-th, N being an integer equal to or larger than three, SIMD arithmetic elements respectively including:
• first operand registers to which the first operand data is input;
• second operand registers to which the second operand data is input;
• arithmetic operators configured to receive inputs of the first operand data and second operand data and perform an arithmetic operation of the first operand data and second operand data;
• and
• result registers configured to store arithmetic results output by the arithmetic operators;
• first to N-th element circuits respectively including:
• input circuits configured to input first operand data and second operand data;
• element data selectors configured to select operand data of any of element circuits on the basis of a request element signal;
• and
• mask selectors configured to select outputs of the element data selectors or all-zero data;
• and
• a data bus configured to supply the operand data input by the element circuits from the input circuits of the element circuits to the element data selectors of the element circuits, wherein
• the element data selectors in the first to N-th element circuits respectively select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits, and
• the mask selectors output the outputs of the element data selectors or the all-zero data selected by the mask selectors to the result registers.

A control method for an arithmetic circuit including:

• first to N-th, N being an integer equal to or larger than three, SIMD arithmetic elements respectively including:
• first operand registers to which the first operand data is input;
• second operand registers to which the second operand data is input;
• arithmetic operators configured to receive inputs of the first operand data and second operand data and perform an arithmetic operation of the first operand data and second operand data;
• and
• result registers configured to store arithmetic results output by the arithmetic operators;
• first to N-th element circuits respectively including:
• input circuits configured to input first operand data and second operand data;
• element data selectors configured to select operand data of any of element circuits on the basis of a request element signal;
• and
• mask selectors configured to select outputs of the element data selectors or all-zero data;
• and
• a data bus configured to supply the operand data input by the element circuits from the input circuits of the element circuits to the element data selectors of the element circuits,
• the method comprising:
• selecting the first operand data of any of the element circuits on the basis of the request element signal included in the second operand data by the element data selectors respectively included in the first to N-th element circuits, and
• outputting the outputs of the element data selectors or the all-zero data selected by the mask selectors to the result registers.