Symbol lock method and a memory system using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHYE-RAN KIM, TAE-YOUNG OH
Life of this patent
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Abstract
A memory system includes a transmitter and a receiver. The transmitter is configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface. The data burst includes a first data and a subsequent data. The receiver is configured to receive the data signal, to detect the first symbol lock pattern based on the received data signal, and to find the first data of the data burst according to the detected first symbol lock pattern.
Claims25
A memory system comprising:
- a transmitter configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface, the data burst having a first data and a subsequent data;
- and
- a receiver configured to receive the data signal, detect the first symbol lock pattern based on the received data signal, and find the first data of the data burst according to the detected first symbol lock pattern.
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A memory device comprising:
- a command decoder configured to generate a write enable signal in response to a write command;
- a sampler and write first-input first-output (FIFO) configured to receive and output a write data burst and a data signal corresponding to a first symbol lock pattern according to a clock signal, the write data burst having a first data and a subsequent data;
- and
- a symbol lock pattern detector configured to find the first data of the write data burst based on the write enable signal.
15-19. (canceled)
A memory device comprising:
- a sampler and write first-in first out (FIFO) configured to receive and output a data signal corresponding to a first symbol lock pattern and a write data burst according to a clock signal, the write data burst having a first data and a subsequent data;
- and
- a symbol lock pattern detector configured to store a plurality of second symbol lock patterns, detect the first symbol lock pattern by comparing an output of the sampler and write FIFO with each of the stored second symbol lock patterns, generate a write enable signal according to the detected first symbol lock pattern, and find the first data of the write data burst according to the write enable signal.
24-29. (canceled)
A memory system comprising:
- a memory controller configured to transmit a write command, a data signal corresponding to a first symbol lock pattern, and a data burst having a first data and a subsequent data;
- and
- a memory device configured to receive the write command, the data signal, and the data burst, generate a write enable signal in response to the write command, detect the first symbol lock pattern in response to the write enable signal, and find the first data of the data burst based on the detected first symbol lock pattern.
Dependencies are inferred from the claim text.