Methods and apparatus for managing power with an inter-processor communication link between independently operable processors

#A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.

#The disclosure relates generally to the field of electronics devices, as well as networks thereof. More particularly, in one exemplary aspect, the disclosure is directed to methods and apparatus for implementing an inter-processor communication (IPC) link between two (or more) independently operable processors. Various aspects of the present disclosure are directed to, inter alia, run time processing, power management, boot sequencing and error handling.

#Various bus architectures and techniques have evolved over time which are able to handle increasingly faster data rates, and to provide higher levels of data throughput. One such example is Peripheral Component Interconnect Express (PCIe); see e.g., PCI Express Base Specification Revision 3.1 dated Oct. 8, 2014, which is incorporated herein by reference in its entirety. PCIe is a high-speed serial computer expansion bus standard designed to replace older PCI and similar bus standards. Consistent with the foregoing, PCIe has historically been used as serial computer expansion bus technology, and has had limited applicability beyond such applications.

#FIG. 1 is a logical block diagram of one exemplary apparatus useful for illustrating various principles described herein.

#FIG. 2 is a logical block diagram of one exemplary physical bus interface useful in conjunction with the various principles described herein.

#FIG. 3 is a logical representation of a shared memory interface configured to enable host assisted boot sequencing, in accordance with one implementation of the present disclosure.

#All Figures© Copyright 2014-2015 Apple Inc. All rights reserved.

#Reference is now made to the drawings, wherein like numerals refer to like parts throughout.

#Exemplary embodiments of the present disclosure are now described in detail. While these embodiments are primarily discussed in the context of an inter-processor communication (IPC) link (for example, of the type described within commonly owned and co-pending U.S. patent application Ser. No. 14/856,283 entitled “METHODS AND APPARATUS FOR AGGREGATING PACKET TRANSFER OVER A VIRTUAL BUS INTERFACE”, filed Sep. 16, 2014, previously incorporated by reference in its entirety), it will be recognized by those of ordinary skill that the present disclosure is not so limited. In fact, the various aspects of the disclosure are useful in any device or network of devices that is configured to incorporate and coordinate multiple independent processing elements, as is disclosed herein.