Memory system and memory controller

A memory controller which controls a non-volatile first memory including a memory cell array and a buffer, the memory cell array including a plurality of memory cells, the memory controller comprising:

• a volatile second memory;
• a first control unit which communicates with a host;
• a second control unit configured to
• load information stored in the first memory into the second memory,
• when shifting from a normal mode to a sleep mode, create parity from the information loaded in the second memory, store the created parity and the information loaded in the second memory into the buffer of the first memory, and issue a power supply shutdown request;
• and
• a power supply circuit which shuts down power supply to the second memory and the second control unit in response to the issued power supply shutdown request.