Providing Per Core Voltage And Frequency Control

#Power and thermal management issues are considerations in all segments of computer-based systems. While in the server domain, the cost of electricity drives the need for low power systems, in mobile systems battery life and thermal limitations make these issues relevant. Optimizing a system for maximum performance at minimum power consumption is usually done using the operating system (OS) or system software to control hardware elements. Most modern OS's use the Advanced Configuration and Power Interface (ACPI) standard, e.g., Rev. 3.0b, published Oct. 10, 2006, for optimizing the system in these areas. An ACPI implementation allows a processor core to be in different power-saving states (also termed low power or idle states), generally referred to as so-called C1 to Cn states. Similar package C-states exist for package-level power savings but are not OS-visible.

#When a core is active, it runs at a so-called C0 state, and when the core is idle, it may be placed in a core low power state, a so-called core non-zero C-state. The core C1 state represents the low power state that has the least power savings but can be entered and exited almost immediately, while an extended deep-low power state (e.g., C3) represents a power state where the static power consumption is negligible, but the time to enter/exit this state and respond to activity (i.e., back to C0) is longer.

#In addition to power-saving states, performance states or so-called P-states are also provided in ACPI. These performance states may allow control of performance-power levels while a core is in an active state (C0). In general, multiple P-states may be available, namely from P0-PN. In general, the ACPI P-state control algorithm is to optimize power consumption without impacting performance. The state corresponding to P0 may operate the core at a maximum voltage and frequency combination for the core, while each P-state, e.g., P1-PN, operates the core at different voltage and/or frequency combinations. In this way, a balance of performance and power consumption can occur when the processor is active based on utilization of the processor. While different P-states can be used during an active mode, there is no ability for independent P-states for different cores operating at different voltages and frequencies of a multi-core processor, and accordingly, optimal power savings cannot be attained while achieving a desired performance level, since at best all active cores may be able to operate at different frequencies but they all must share the same voltage.

#FIG. 1 is a block diagram of a system in accordance with one embodiment of the present invention.

#FIG. 2 is a flow diagram of a method in accordance with one embodiment of the present invention.

#FIG. 3 is a flow diagram of a method in accordance with another embodiment of the present invention.

#In various embodiments, a processor having a multi-core architecture may provide for per core control of power-performance (P)-states, e.g., in accordance with an ACPI specification. In this way, better control over power consumption and performance can be realized. For example, in a multi-core processor only a few cores may be enabled to run at a higher core frequency in a thermally constrained environment, enabling execution of a desired workload while reducing power consumption and thus temperature.

#Thus in various embodiments, each of multiple cores within a processor may be controlled to operate at a different voltage and/or frequency. In this way, asymmetric workloads may be executed on the multiple cores to provide for deterministic performance. While the scope of the present invention is not limited in this regard, in some embodiments the independent voltage/frequency control may be realized using a fully integrated voltage regulator (FIVR) implementation in which each core within a processor has its own voltage regulator. That is, a single semiconductor die that includes multiple cores may further include multiple independent voltage regulators, each associated with a given core. Furthermore, one or more additional voltage regulators may be provided for use with other components within a processor such as uncore logic, memory controller logic, power control unit, and so forth. Of course, in some embodiments a single voltage regulator may be associated with one or more cores and/or other components of a processor. In one embodiment, a dedicated voltage regulator may be provided for uncore circuitry of a processor, which would allow the uncore to run at a different voltage and frequency. For a compute centric workload, the uncore can be run at a lower voltage and frequency, resulting in applying power savings toward higher core frequencies at a socket level. For memory and IO intensive workloads, the uncore can be run at a higher voltage and frequency, while the cores can run at lower voltages/frequencies, compensating for higher power in the uncore.

#In some embodiments, ACPI tables may be extended to include information regarding these individual integrated voltage regulators to enable per core P-state control. For example, a 4-bit field may be used to pass P-state information and map it to control voltage logic for each regulator. Thus using embodiments of the present invention, each core may be controlled to operate at a different frequency and/or voltage for an asymmetric workload. As one example, one or a few of multiple cores can be controlled to operate at higher frequencies and/or voltages while the remaining cores are controlled to operate at lower voltage/frequency combinations to thus stay within a given thermal design power (TDP) envelope. In this way, deterministic and optimal performance capability selection can be realized for given workloads.