Bang-Bang Time to Digital Converter Systems and Methods

A time to digital converter comprising:

• a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock;
• and
• a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse,
• wherein the mutual exclusion element includes cross coupled NAND gates and a metastability filter coupled to the cross coupled NAND gates.

A time to digital converter comprising:

• a mutual exclusion element configured to receive a first clock and a second clock and to generate a first pulse and a second pulse, wherein the mutual exclusion element is configured to drive the first pulse to a first logic state and the second pulse to a second logic state upon the first clock being earlier than the second clock and drive the second pulse to the first logic state and the first pulse to the second logic state upon the second clock being earlier than the first clock;
• and
• a sampling component configured to receive the first pulse and the second pulse and to generate a decision signal according to the first pulse and the second pulse,
• wherein the sampling component includes a first stage of delay flops and a second stage of delay flops.

A digital frequency system comprising:

• a first path having a first delay and configured to generate a first clock, the first clock having a first frequency;
• a second path having a second delay and configured to generate a second clock, the second clock having a second frequency;
• a time to digital converter configured to generate a decision signal based on the first clock and the second clock, wherein the decision signal indicates which of the first clock and the second clock is earlier;
• and
• a loop component configured to receive the decision signal and generate a calibration signal based on the decision signal.

A method of generating a timing decision signal, the method comprising:

• generating a first clock signal by a first path;
• generating a second clock signal by a second path;
• generating a first pulse and a second pulse by a mutual exclusion element, wherein the first pulse is set to a first logic state upon the first clock signal being earlier and the second pulse is set to the first logic state upon the second clock signal being earlier;
• and
• generating a decision signal by a sampling component indicating which of the first and second clocks is earlier based on the first pulse and the second pulse.