Current mode logic circuit for high speed input/output applications

A method comprising:

• receiving, at an input stage of a current mode logic (CML) latch, a differential input signal;
• providing, from the input stage, a differential intermediate output signal in response to receiving the differential input signal;
• increasing, by a negative resistance stage of the CML latch coupled to the input stage, a current gain of the differential intermediate output signal;
• latching, by a latch stage of the CML latch, the differential intermediate output signal;
• and
• providing, from the latch stage, a differential output signal based upon the latched differential intermediate output signal.

A current mode logic (CML) latch comprising:

• an input stage including a positive input node to receive a positive side of a differential input signal, a negative input node to receive a negative side of the differential input signal, a positive output node to provide a positive side of a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal;
• a negative resistance stage including:
• a first transistor of a first conductivity type, including a first current electrode connected to a first voltage source, a control electrode connected to the negative output node of the input stage, and a second electrode connected to the positive output node of the input stage;
• and
• a second transistor of the first conductivity type, including a first current electrode connected to the first voltage source, a control electrode connected to the positive output node of the input stage, and a second current electrode connected to the negative output node of the input stage;
• and
• a latch stage including:
• a third transistor of a first conductivity type, including a first current electrode connected to the first voltage source, a control electrode connected to the positive output node of the input stage, and a second current electrode;
• a first resistive element including a first electrode connected to the positive output node of the input stage and a second electrode connected to the second current electrode of the third transistor;
• a fourth transistor of a second conductivity type, including a first current electrode connected to the second current electrode of the third transistor and to the second electrode of the first resistive element, a control electrode connected to the positive output node of the input stage, and a second current electrode coupled to a second voltage source, wherein the positive output node of the latch stage comprises the second current electrode of the third transistor, the first current electrode of the fourth transistor and the second electrode of the first resistive element;
• a fifth transistor of the first conductivity type, including a first current electrode connected to the first voltage source, a control electrode connected to the negative output node of the input stage, and a second current electrode;
• a second resistive element including a first electrode connected to the negative output node of the input stage and a second electrode connected to the second current electrode of the fifth transistor;
• and
• a sixth transistor of the second conductivity type, including a first current electrode connected to the second current electrode of the fifth transistor and to the second electrode of the second resistive element, a control electrode connected to the negative output node of the input stage, and a second current electrode coupled to the second voltage source, wherein the negative output node of the latch stage comprises the second current electrode of the fifth transistor, the first current electrode of the sixth transistor and the second electrode of the second resistive element.