# US 2016/0099206 A1 · Wafer level packaging of electronic device

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- Number: US 2016/0099206 A1
- Document ID: US20160099206A1
- Status: Published application
- Kind: A1
- Application number: 14/872,646
- Filed: 2015-10-01
- Published: 2016-04-07
- Earliest claimed: 2014-10-06
- Assignees: Viagan Ltd.
- Applicants: VIAGAN Ltd.
- Inventors: Mordechai Margalit
- Web page: https://patentgrep.com/patent/US20160099206A1

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 70/69: Insulating materials thereof
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Wafer level packaged semiconductor device with enhanced heat dissipation properties. The semiconductor device includes a top and a bottom face and at least one metal pad is positioned on the top and the bottom faces. A top cover is affixed to the top face of the semiconductor device and a bottom cover is affixed to the bottom face of the semiconductor device. Vias extend through the top and bottom covers and an electroplated metal layer extends from an external face of the covers, through the visas to the metal pads on the semiconductor device.

## Claims

### Claim 1

A wafer level packaging of semiconductor devices comprising:
a semiconductor device with a top face and bottom face and at least one metal pad located on top and bottom face and;
a top cover wafer affixed to the top face of semiconductor device and;
a bottom cover wafer affixed to the bottom face of semiconductor device; whereas the top and bottom cover wafers have vias extending from an external face of each cover wafer to internal face of said cover wafer; and wherein an electroplated metal layer extends from the external face of each cover wafer through the via to the metal pad.

### Claim 2 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one metal pad is an electrical pad.

### Claim 3 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one metal pad is a thermal pad.

### Claim 4 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one cover wafer is one of a Silicon, Glass, Quartz, Ceramic, Metal, Glass fiber and Epoxy, polymer wafer.

### Claim 5 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one cover wafer is electrically isolating.

### Claim 6 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one cover wafer has an electrically isolating layer on at least one side of the wafer, said electrically isolating layer can be one of a group of electrically isolating layers consisting of: SiO2, SiN, Epoxy, Silicone and polyamide.

### Claim 7 (depends on 1)

The wafer level packaging of semiconductor devices of claim 1, wherein at least one via has an electrically isolating layer on a side wall of the via electrically isolating the electroplated metal layer from the cover wafer, said electrically isolating layer can be one of: SiO2, SiN, epoxy, Silicone and polyamide.

### Claim 8

A method of wafer level packaging of semiconductor devices comprising:
attaching multiple semiconductor devices to a bottom wafer, wherein each of the semiconductor devices includes at least one metal pad on a top surface of each semiconductor device and at least one metal pad on a bottom surface of each semiconductor device;
applying an encapsulation layer over the semiconductor devices and the bottom wafer;
attaching a top wafer over the encapsulation layer;
creating vias in the top wafer, wherein the vias in the top wafer extend from an external surface of the top wafer to the metal pads on the top surface of each semiconductor device;
creating vias in the bottom wafer, wherein the vias in the bottom wafer extend from an external surface of the bottom wafer to the metal pads on the bottom surface of each semiconductor device; and
electroplating a metal layer to connect the metal pads of the semiconductor devices, through the via to an external face of the top or bottom wafer.

### Claim 9

A wafer level packaging for semiconductor devices, wherein the semiconductor device includes a top face and a bottom face and one or more metal pads located on the top face or the bottom face, the wafer level packaging comprising:
a first wafer cover that includes an external face and an internal face, the first wafer cover is affixed to the top face of semiconductor device by mating the internal face of the first wafer cover to the top face of the semiconductor device;
a second wafer cover that includes an external face and an internal face, the second wafer cover is affixed to the bottom face of semiconductor device by mating the internal face of the second wafer cover to the bottom face of the semiconductor device;
the first wafer cover including one or more apertures that extend from the external face of the first wafer cover to the internal face of the first wafer cover, wherein at least one of the one or more apertures aligns with at least one of the one or more metal pads located on the top face of the semiconductor device;
the second wafer cover including one or more apertures that extend from the external face of the second wafer cover to the internal face of the second wafer cover, wherein at least one of the one or more apertures aligns with at least one of the one or more metal pads located on the bottom face of the semiconductor device; and
wherein an electroplated metal layer extends from the external face of the first wafer cover wafer through the aperture to the at least one metal pad on the top surface of the semiconductor device and an electroplated metal layer extends from the external face of the second wafer cover wafer through the aperture to the at least one metal pad on the bottom surface of the semiconductor device.