Hierarchical fill in a design layout
AssigneeMentor Graphics Corporation
InventorsFedor Pikus, Jimmy Jason Tomblin, William S. Graupp
Life of this patent
Estimating the term…
Abstract
This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
Claims20
A method comprising:
- capturing, by a computing system, a hierarchy of a circuit design layout generated by a downstream tool, wherein the hierarchy includes multiple cells, each identifying a different portion of the circuit design layout;
- and
- modifying, by the computing system, the circuit design layout based, at least in part, on the captured hierarchy, which alters portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
A system comprising:
- a memory system configured to store computer-executable instructions;
- and
- a computing system, in response to execution of the computer-executable instructions, is configured to:
- capture a hierarchy of a circuit design layout generated by a downstream tool, wherein the hierarchy includes multiple cells, each identifying a different portion of the circuit design layout;
- and
- modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
- capturing, by a computing system, a hierarchy of a circuit design layout generated by a downstream tool, wherein the hierarchy includes multiple cells, each identifying a different portion of the circuit design layout;
- and
- modifying, by the computing system, the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout.
Dependencies are inferred from the claim text.