Matrix reduction for lithography simulation
AssigneeSynopsys, Inc.
InventorThomas Christopher Cecil
Life of this patent
Estimating the term…
Abstract
A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.
Claims21
A computer program product embodied in a non-transitory computer readable medium for design analysis, the computer program product comprising:
- code for identifying, from the mask data based on a semiconductor design, target points and moveable mask edges;
- code for determining interactions between the moveable mask edges wherein the interactions impact a resulting semiconductor fabrication shape;
- code for building a graph that shows the interactions;
- code for partitioning the graph into a plurality of groups, based on the interactions;
- and
- code for performing lithography simulations based on the plurality of groups.
2-24. (canceled)
A computer-implemented method for design analysis comprising:
- identifying, from the mask data based on a semiconductor design, target points and moveable mask edges;
- determining interactions between the moveable mask edges wherein the interactions impact resulting semiconductor fabrication shapes;
- building a graph that shows the interactions;
- partitioning the graph into a plurality of groups, based on the interactions;
- and
- performing lithography simulations based on the plurality of groups.
A computer system for design analysis comprising:
- a memory which stores instructions;
- one or more processors coupled to the memory wherein the one or more processors are configured to:
- identify, from the mask data based on a semiconductor design, target points and moveable mask edges;
- determine interactions between the moveable mask edges wherein the interactions impact a resulting semiconductor fabrication shape;
- build a graph that shows the interactions;
- partition the graph into a plurality of groups, based on the interactions;
- and
- perform lithography simulations based on the plurality of groups.
Dependencies are inferred from the claim text.