Integrated circuit and method of designing layout of integrated circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsJAE-WOO SEO, HA-YOUNG KIM, HYUN-JEONG ROH
Life of this patent
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Abstract
A method of designing a layout of an integrated circuit (IC) includes placing a first cell in the layout, placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells, and generating a plurality of commands executable by a processor to form a semiconductor device based on the layout. The first cell includes a first pattern and a second pattern. The first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary.
Claims21
A method of designing a layout of an integrated circuit (IC), comprising:
- placing a first cell in the layout, wherein the first cell comprises a first pattern and a second pattern;
- placing a second cell in the layout adjacent to the first cell at a first boundary between the first and second cells,
- wherein the first and second patterns are adjacent to the first boundary, the first and second patterns have different colors, and a first boundary space between the first pattern and the first boundary is different from a second boundary space between the second pattern and the first boundary;
- and
- generating a plurality of commands executable by a processor to form a semiconductor device based on the layout.
16-23. (canceled)
An integrated circuit (IC), comprising:
- a plurality of cells;
- and
- a plurality of patterns disposed in each of the plurality of cells and adjacent to a boundary at each of the plurality of cells,
- wherein the plurality of patterns have different colors corresponding respectively to different masks, and respective boundary spaces between the patterns and the boundary are different from one another.
26-27. (canceled)
A method of manufacturing a semiconductor device, comprising:
- placing a first cell in a layout, wherein the first cell comprises at least two patterns disposed adjacent to a first boundary between the first cell and a second cell;
- placing the second cell in the layout adjacent to the first cell at the first boundary, wherein the first and second cells are among a plurality of cells that defines an integrated circuit (IC),
- wherein the at least two patterns have different colors and respective boundary spaces between the at least two patterns and the first boundary are different from each other;
- and
- forming the semiconductor device based on the layout, wherein the semiconductor device is formed using a multi-patterning operation performed on the at least two patterns using different masks corresponding respectively to the different colors.
29-30. (canceled)
Dependencies are inferred from the claim text.