Signal delay flip-flop cell for fixing hold time violation

A method of adjusting hold timing in design of an integrated circuit (IC) including logic cells and flip-flop cells using an electronic design automation (EDA) tool, wherein the flip-flop cells are connected with the logic cells in a combination in a functional mode of operation, and are connected together in series in a scan test mode of operation by a scan control signal for shifting scan test data into the IC, the method comprising:

• identifying liability to scan test data hold violation in at least a problematic one of the flip-flop cells;
• and
• replacing the problematic flip-flop cell by a signal delay cell that has a first multiplexer having a first data input node, a scan data input node and a first output node, a second multiplexer having a second data input node, a second input node connected to the first output node, and a second output node, and a flip-flop module having a data input connected to the second output node, a clock input node and a flip-flop output node,
• wherein the propagation of a scan data input signal applied to the scan data input node in the scan test mode of operation is delayed, and the hold margin of the flip-flop module for the scan data input signal is increased by transit through the first multiplexer.

A non-transitory computer-readable storage medium storing instructions for execution by an electronic design automation (EDA) tool including a processor and a memory coupled to the processor which, when executed by the EDA tool, cause the EDA tool to perform a method of adjusting hold timing in an integrated circuit (IC) design stored in the memory, the IC design including logic cells and flip-flop cells, wherein the flip-flop cells are connected with the logic cells in a combination in a functional mode of operation, and are connected together in series in a scan test mode of operation by a scan control signal for shifting scan test data into the IC, the method comprising:

• identifying liability to a scan test data hold violation in at least a problematic one of the flip-flop cells;
• and
• replacing the problematic flip-flop cell by a signal delay cell that has a first multiplexer having a first data input node, a scan data input node and a first output node, a second multiplexer having a second data input node, a second input node connected to the first output node, and a second output node, and a flip-flop module having a data input connected to the second output node, a clock input node and a flip-flop output node,
• wherein the propagation of a scan data input signal applied to the scan data input node in the scan test mode of operation is delayed, and the hold margin of the flip-flop module for the scan data input signal is increased by transit through the first multiplexer.