Efficient emulation and logic analysis
AssigneeSynopsys, Inc.
InventorLUDOVIC MARC LARZUL
Life of this patent
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Abstract
An emulation environment includes a host system and an emulator. The host system configures the emulator to load a design under test (DUT) and the emulator emulates the DUT. The emulator includes one or more design field-programmable gate arrays (FPGAs) that emulate the DUT. In addition, the emulator includes at least one system FPGA with a logic analyzer and multiple virtual FPGA. The virtual FPGAs emulate sections of the DUT. By the virtual FPGAs emulating sections of the DUT, the logic analyzer is able to obtain for performing logic analysis certain signals from the virtual FPGAs, rather than from the design FPGAs.
Claims20
An emulator comprising:
- a plurality of design field-programmable gate arrays (FPGAs) configured to collectively emulate a design under test (DUT) and produce a first signal of the DUT, the DUT including a first section;
- and
- a system FPGA comprising:
- a plurality of computational blocks, at least one of the plurality of computational blocks configured to emulate a second section of the DUT and produce a second signal of the DUT based on the first signal, the second section substantially similar to the first section, and
- a logic analyzer configured to perform logic analysis based on the second signal.
A non-transitory computer readable medium storing instructions, the instructions to configure an emulator to:
- emulate a first section of a design under test (DUT);
- produce a first signal based on the emulation of the first section;
- emulate a second section of the DUT based on the first signal, the second section substantially similar to the first section;
- produce a second signal based on the emulation of the second section;
- and
- perform logic analysis based on the second signal.
A method comprising:
- emulating a first section of a design under test (DUT);
- producing a first signal based on the emulation of the first section;
- emulating a second section of the DUT based on the first signal, the second section substantially similar to the first section;
- producing a second signal based on the emulation of the second section;
- and
- performing logic analysis based on the second signal.
A non-transitory computer readable medium configured to store instructions, the instructions executed by one or more processors for:
- transmitting, by a host system to an emulator, information to configure a plurality of design field-programmable gate arrays (FPGAs) included in the emulator to collectively emulate a design under test (DUT);
- identifying, by the host system, a plurality of signals of the DUT used by a system FPGA included in the emulator in performing logic analysis during emulation of the DUT;
- selecting, by the host system from a plurality of computational blocks included in the system FPGA, a subset of computational blocks to configure for the emulation of the DUT, the subset of computational blocks selected based on the identified plurality of signals;
- and
- transmitting, by the host system to the emulator, information to configure the computational blocks in the subset for the emulation, at least one of the computational blocks in the subset configured based on the information to generate a signal from the plurality of signals during the emulation.
Dependencies are inferred from the claim text.