Efficient power analysis

A power analysis logic comprising:

• a multiplexer configured to:
• receive a plurality of signals of a design under test (DUT) being emulated by an emulator, and
• select a signal from the plurality of signals;
• an event detector configured to determine whether a state event is detected for the selected signal;
• and
• an accumulator configured to increment a state count associated with the selected signal in response to the state event being detected for the selected signal, the state count indicating a number of state events detected for the selected signal during emulation of the DUT,
• the power analysis logic structured to be incorporated into the DUT prior to the emulation of the DUT for emulation during the emulation of the DUT.

A non-transitory computer readable medium configured to store instructions, the instructions when executed by at least one processor to:

• receive, by a host system, a description of a design under test (DUT) to be emulated by an emulator;
• incorporate, by the host system into the description of the DUT, power analysis logic configured to track states of a plurality of signals of the DUT during emulation of the DUT;
• transmit, by the host system to the emulator, information associated with the DUT with the power analysis logic incorporated for emulation of the DUT;
• maintain, by the host system for each of the plurality of signals at least one aggregate count indicating a total number of state events detected for a signal from the plurality of signals during emulation of the DUT;
• and
• update, by the host system, the aggregate count maintained for the signal from the plurality of signals, responsive to receiving a count update signal indicating that a state count maintained by the emulator for the signal reached a threshold number, the count update signal received based on emulation of the power analysis logic.

A method comprising:

• receiving, by a host system, a description of a design under test (DUT) to be emulated by an emulator;
• incorporating, by the host system into the description of the DUT, power analysis logic configured to track states of a plurality of signals of the DUT during emulation of the DUT;
• transmitting, by the host system to the emulator, information associated with the DUT with the power analysis logic incorporated for emulation of the DUT;
• maintaining, by the host system for each of the plurality of signals at least one aggregate count indicating a total number of state events detected for a signal from the plurality of signals during emulation of the DUT;
• and
• updating, by the host system, the aggregate count maintained for the signal from the plurality of signals, responsive to receiving a count update signal indicating that a state count maintained by the emulator for the signal reached a threshold number, the count update signal received based on emulation of the power analysis logic.

A method executed by an emulator for tracking signals of a design under test (DUT), the method comprising:

• receiving a plurality of signals of a DUT being emulated;
• selecting a signal from the plurality of signals;
• determining whether a state event is detected for the selected signal;
• and
• incrementing a state count associated with the selected signal in response to the state event being detected for the selected signal, the state count indicating a number of state events detected for the selected signal during emulation of the DUT.