US 2016/0098364 A1 · RECONFIGURABLE HARDWARE STRUCTURES FOR FUNCTIONAL PIPELINING OF ON-CHIP SPECIAL PURPOSE FUNCTIONS

Abstract

A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory. Consequently, a program that utilizes the method or apparatus, reduces power consumption, consumes less memory bandwidth, and reduces the program's memory footprint.

Claims20

Dependent claims

A device comprising:

a first multiplexer operatively coupled between a first streaming functional unit and a first plurality of potential input sources;
a second multiplexer operatively coupled between a second streaming functional unit and a second plurality of potential input sources;
wherein output of the first streaming functional unit is one potential input source, of the second plurality of potential input sources;
a scheduler configured to:
determine how to configure the first multiplexer and second multiplexer to make use of the first streaming functional unit and the second streaming functional unit in processing data;
and
send signals to dynamically configure the first multiplexer and second multiplexer to make use of the first streaming functional unit and the second streaming functional unit in processing the data.

4 more elements

A system comprising:

a memory;
a processor coupled to the memory;
and
a specialized coprocessor, coupled to the processor and the memory, wherein the specialized coprocessor comprises:
a first multiplexer operatively coupled between a first streaming functional unit and a first plurality of potential input sources;
a second multiplexer operatively coupled between a second streaming functional unit and a second plurality of potential input sources;
wherein output of the first streaming functional unit is one potential input source, of the second plurality of potential input sources;
wherein the specialized coprocessor is configured to:
determine how to configure the first multiplexer and second multiplexer to make use of the first streaming functional unit and the second streaming functional unit in processing data;
and
send signals to dynamically configure the first multiplexer and second multiplexer to make use of the first streaming functional unit and the second streaming functional unit in processing the data.

8 more elements

Dependencies are inferred from the claim text.

Reconfigurable hardware structures for functional pipelining of on-chip special purpose functions

Life of this patent

Reconfigurable hardware structures for functional pipelining of on-chip special purpose functions

Life of this patent

Abstract

Claims20