Error processing method, memory storage device and memory controlling circuit unit

A memory storage device, comprising:

• a connection interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of memory cells;
• and
• a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells,
• the memory controlling circuit unit is further configured to perform a first decoding on the bits,
• if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one error belongs to a first type error or a second type error,
• if a first error in the at least one error belongs to the first type error, the memory controlling circuit unit is further configured to record related information of the first error, and
• if the first error belongs to the second type error, the memory controlling circuit unit does not record the related information of the first error.

A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises:

• a host interface, configured to couple to a host system;
• a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells;
• an error checking and correcting circuit;
• and
• a memory management circuit coupled to the host interface, the memory interface and the error checking and correcting circuit,
• wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from the memory cells,
• the error checking and correcting circuit is configured to perform a first decoding on the bits,
• if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one error belongs to a first type error or a second type error,
• if a first error in the at least one error belongs to the first type error, the memory management circuit is further configured to record related information of the first error, and
• if the first error belongs to the second type error, the memory management circuit does not record the related information of the first error.

An error processing method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the error processing method comprising:

• sending a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells;
• performing a first decoding on the bits;
• if the bits have at least one error, correcting the at least one error, and determining whether each of the at least one error belongs to a first type error or a second type error;
• if the at least one error includes the first type error, sending a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells;
• and
• if each of the at least one error belongs to the second type error, outputting the corrected bits,
• wherein the first memory cell is different from the second memory cell.

A memory storage device, comprising:

• a connection interface unit, configured to couple to a host system;
• a rewritable non-volatile memory module comprising a plurality of memory cells;
• and
• a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory controlling circuit unit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells,
• the memory controlling circuit unit is further configured to perform a first decoding on the bits,
• if the bits have at least one error, the memory controlling circuit unit is further configured to correct the at least one error and determine whether each of the at least one error belongs to a first type error or a second type error,
• if the at least one error includes the first type error, the memory controlling circuit unit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and
• if each of the at least one error belongs to the second type error, the memory controlling circuit unit is further configured to output the corrected bits,
• wherein the first memory cell is different from the second memory cell.

A memory controlling circuit unit, configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory controlling circuit unit comprises:

• a host interface, configured to couple to a host system;
• a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells;
• an error checking and correcting circuit;
• and
• a memory management circuit, coupled to the host interface, the memory interface and the error checking and correcting circuit,
• wherein the memory management circuit is configured to send a first read command sequence, wherein the first read command sequence is configured to read a plurality of bits from a first memory cell in the memory cells,
• the error checking and correcting circuit is configured to perform a first decoding on the bits,
• if the bits have at least one error, the error checking and correcting circuit is further configured to correct the at least one error and the memory management circuit is further configured to determine whether each of the at least one error belongs to a first type error or a second type error,
• if the at least one error includes the first type error, the memory management circuit is further configured to send a write command sequence, wherein the write command sequence is configured to write the corrected bits into a second memory cell in the memory cells, and
• if each of the at least one error belongs to the second type error, the memory management circuit is further configured to output the corrected bits,
• wherein the first memory cell is different from the second memory cell.