Method and apparatus for segmented sequential storage
AssigneeSearete LLC
InventorAndrew F. Glew
Life of this patent
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Abstract
Various embodiments are described relating to processors, hierarchical processors, branch predictors, branch prediction systems, and computing systems. Some or all of a hierarchical instruction scheduler, hierarchical register file, or a hierarchical store buffer may be included in a hierarchical microprocessor. Some or all aspects of the hierarchical microprocessor may be implemented, partially or fully, using a method for sequential data storage.
Claims24
(canceled)
A processor comprising:
- a plurality of branch predictors, wherein each branch predictor is adapted to provide a prediction and an override signal;
- and
- a branch prediction control circuit adapted to generate a branch prediction based on the prediction and the override signal from each predictor,
- wherein the override signal of a particular predictor results in one of (i) the prediction of the particular predictor being accepted by the processor regardless of the predictions of the other predictors and (ii) the prediction of the particular predictor not being accepted by the processor regardless of the prediction of the particular predictor.
-25. (canceled)
A method for processing instructions in a microprocessor, the method comprising:
- receiving instructions for execution at a first-level instruction scheduler;
- storing first operand status information for respective operands of the instructions;
- dispatching, based on the first operand status information, the instructions to respective execution clusters of the microprocessor, wherein each of the respective execution clusters includes a corresponding second-level instruction scheduler, the second-level instruction schedulers being operatively coupled with the first-level instruction scheduler;
- receiving, at the second-level instruction schedulers, the instructions from the first-level instruction scheduler;
- storing second operand status information for respective operands of the instructions;
- dispatching, based on the second operand status information, the instructions to respective execution units of the execution clusters;
- and
- executing one of more of the instructions.
-100. (canceled)
An apparatus comprising a non-transitory machine readable medium having instructions stored thereon, the instructions, when executed by a processor, provide for at least:
- dividing a non-circular data structure into a plurality of segments, each segment including a plurality of entries;
- dynamically allocating the plurality of segments;
- and
- sequentially associating the dynamically allocated segments.
-137. (canceled)
Dependencies are inferred from the claim text.