Compressing instruction queue for a microprocessor
AssigneeVIA Technologies, Inc.
InventorsMATTHEW DANIEL DAY, G. GLENN HENRY, TERRY PARKS
Life of this patent
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Abstract
A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue.
Claims28
A compressing instruction queue for a microprocessor, comprising:
- a queue comprising a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order;
- and
- redirect logic that is configured to receive and write up to P microinstructions per cycle of a clock signal into sequential storage locations of said queue without leaving unused storage locations and beginning at a first available storage location in said queue.
A microprocessor, comprising:
- an instruction translator that is configured to translate a plurality of architectural instructions and to provide up to P microinstructions per clock cycle of a clock signal;
- a compressing instruction queue, comprising:
- a queue comprising a matrix of storage locations including N rows and M columns for storing microinstructions from said instruction translator in a sequential order;
- and
- redirect logic that is configured to receive and write up to P microinstructions per cycle of a clock signal into sequential storage locations of said queue without leaving unused storage locations and beginning at a first available storage location in said queue;
- and
- processing logic that is configured to receive and process microinstructions from said queue one row at a time in program order in a clock cycle.
A method of compressing microinstructions into an instruction queue of a microprocessor, comprising:
- receiving up to P microinstructions from an instruction translator in a clock cycle of a clock signal;
- determining a first available storage location of a queue comprising a matrix of storage locations including N rows and M columns for storing microinstructions in sequential order;
- and
- redirecting the up to P microinstructions per clock cycle towards sequential storage locations of the queue in sequential order beginning at the first available storage location without leaving unused storage locations in the queue.
Dependencies are inferred from the claim text.