Operand conflict resolution for reduced port general purpose register
AssigneeQUALCOMM Incorporated
InventorsYun Du, Hongjiang Shang, Haikun Zhu
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Abstract
Techniques are described for determining whether execution of an instruction would require reading more values from a memory cell of a general purpose register (GPR) than a read port of the memory cell would allow. In such a case, the techniques may store, prior to execution of the instruction, one or more values from the memory cell in a separate conflict queue. During execution of the instruction to implement an operation defined by the instruction, one value that is an operand of the operation would be read from the memory cell and another value that is an operand of the operation other would be read from the conflict queue.
Claims23
A method of processing values, the method comprising:
- determining whether execution of an instruction would cause simultaneous reading of more values from a first memory cell of a plurality of memory cells of a general purpose register (GPR) than a read port of the first memory cell can output, wherein values stored in the first memory cell cannot be accessed via any of the other memory cells of the GPR;
- prior to execution of the instruction, storing one or more values stored in the first memory cell in a conflict queue separate from the GPR based on the determination that execution of the instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- and
- executing the instruction to implement an operation defined by the instruction that uses at least one value from the first memory cell and at least one value from the conflict queue as operands.
A device for processing value, the device comprising:
- a general purpose register (GPR) comprising a plurality of memory cells that includes a first memory cell having a read port, wherein values stored in the first memory cell cannot be accessed via any of the other memory cells of the GPR;
- and
- a graphics processing unit (GPU) configured to:
- determine whether execution of an instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- prior to execution of the instruction, store one or more values stored in the first memory cell in a conflict queue separate from the GPR based on the determination that execution of the instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- and
- execute the instruction to implement an operation defined by the instruction that uses at least one value from the first memory cell and at least one value from the conflict queue as operands.
A computer-readable storage medium having instructions stored thereon that when executed by one or more processors cause the one or more processors to:
- determine whether execution of an instruction would cause simultaneous reading of more values from a first memory cell of a plurality of memory cells of a general purpose register (GPR) than a read port of the first memory cell can output, wherein values stored in the first memory cell cannot be accessed via any of the other memory cells of the GPR;
- prior to execution of the instruction, store one or more values stored in the first memory cell in a conflict queue separate from the GPR based on the determination that execution of the instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- and
- execute the instruction to implement an operation defined by the instruction that uses at least one value from the first memory cell and at least one value from the conflict queue as operands.
A device for processing value, the device comprising:
- a general purpose register (GPR) comprising a plurality of memory cells that includes a first memory cell having a read port, wherein values stored in the first memory cell cannot be accessed via any of the other memory cells of the GPR;
- and
- a graphics processing unit (GPU) comprising:
- means for determining whether execution of an instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- means for storing, prior execution of the instruction, one or more values stored in the first memory cell in a conflict queue separate from the GPR based on the determination that execution of the instruction would cause simultaneous reading of more values from the first memory cell than the read port of the first memory cell can output;
- and
- means for executing the instruction to implement an operation defined by the instruction that uses at least one value from the first memory cell and at least one value from the conflict queue as operands.
Dependencies are inferred from the claim text.