Thermal-aware compiler for parallel instruction execution in processors
AssigneeAdvanced Micro Devices, Inc.
InventorsYuan Xie, Junli Gu
Life of this patent
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Abstract
Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.
Claims22
A method for compiling instruction code for execution in a processor having a plurality of functional units, comprising:
- determining a thermal constraint of the processor;
- and
- scheduling in the compiled instruction code real instructions to be executed in parallel by the plurality of functional units, wherein said scheduling is configured to prevent exceeding the thermal constraint during execution of the instruction code.
A method of allocating resources in a processor having a plurality of functional units when executing instruction code, the method comprising:
- defining a relative importance of each functional unit of the plurality of functional units;
- determining a thermal constraint of the processor;
- defining a plurality of instruction words each containing real instructions and no operation (NOP) instructions to be simultaneously executed by the plurality of functional units during a single respective clock cycle, wherein the real instructions activate a respective functional unit;
- determining if a threshold limit defining the thermal constraint is reached during activation of the functional units;
- and
- de-activating functional units in order of relative importance to maximize performance of the processor.
An apparatus comprising:
- a modeling component determining a thermal constraint of a processor having a plurality of functional units configured to simultaneously execute during a single clock cycle, instructions packed in an instruction word;
- and
- a compiler component defining a plurality of instruction words each comprising both real instructions and one or more no operation (NOP) instructions to be executed by the plurality of functional units in parallel, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.
Dependencies are inferred from the claim text.