Information processor apparatus, memory control device, and control method

A memory control device comprising:

• paths coupled to a storage device;
• and
• a controller configured to supply, through the paths to the storage device, a read request or a write request from an arithmetic processor;
• wherein,
• the controller:
• calculates, for each of the paths, an overall time until the response to a transmitted read request and a transmitted write request is received based on a first number of the transmitted read requests and a second number of the transmitted write requests, the transmitted read request and the transmitted write request having been transmitted to the paths, responses for the transmitted read request and the transmitted write request having not been received,
• selects a used path to be used based on the overall time:
• transmits the read request or the write request through the used path to the storage device and
• receives, from the storage device, the response to the read request or the write request through the used path.

A control method comprising:

• receiving a read request or a write request for a storage device from an arithmetic processor;
• calculating, for each of paths, an overall time until the response to a transmitted read request and a transmitted write request is received based on a first number of the transmitted read requests and a second number of the transmitted write requests, the transmitted read request and the transmitted write request having been transmitted to at least one of the paths among the plurality of paths coupled to the storage device, responses for the transmitted read request and the transmitted write request having not been received:
• selecting, from the paths, a used path to be used based on the overall time;
• transmitting the read request or the write request through the used path to the storage device;
• and
• receiving, from the storage device, the response to the read request or the write request through the used path.