Method and apparatus for determining a timing adjustment of output to a host memory controller
AssigneeIntel Corporation
InventorBill NALE
Life of this patent
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Abstract
Provided are a method and apparatus for determining a timing adjustment of output to a host memory controller in a first memory module coupled to a host memory controller and a second memory module over a bus. A determination is made of a timing adjustment based on at least one component in at least one of the first memory module and the second memory module. A timing of output to the host memory controller is adjusted based on the determined timing adjustment to match a timing of output at the second memory module.
Claims25
A device implemented in a first memory module coupled to a host memory controller and a second memory module over a bus, comprising:
- memory module controller logic to:
- determine a timing adjustment based on at least one component in at least one of the first memory module and the second memory module;
- and
- adjust a timing of output to the host memory controller based on the determined timing adjustment to match a timing of output at the second memory module.
An apparatus comprising:
- a host memory controller;
- a bus;
- a first memory module and a second memory module coupled to the host memory controller over the bus;
- memory module controller logic implemented in the first memory module to:
- determine a timing adjustment based on at least one component in at least one of the first memory module and the second memory module;
- and
- adjust a timing of output to the host memory controller based on the determined timing adjustment to match a timing of output at the second memory module.
A method for determining a timing adjustment for a first memory module coupled to a host memory controller and a second memory module over a bus, comprising:
- determining a timing adjustment based on at least one component in at least one of the first memory module and the second memory module;
- and
- adjust a timing of output to the host memory controller based on the determined timing adjustment to match a timing of output at the second memory module.
Dependencies are inferred from the claim text.