Mechanism for enabling full data bus utilization without increasing data granularity
AssigneeRambus Inc.
InventorBilly Garrett, JR.
Life of this patent
Estimating the term…
Abstract
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.
Claims21
(canceled)
A controller to control the operation of a dynamic random access memory (DRAM) having at least first and second memory portions, wherein each of the first and second memory portions includes
- a plurality of memory banks, the controller comprising:
- logic to control the timing of access requests generated by the controller, the access requests to be sent to the first and second portions of the DRAM such that a delay time between consecutive access requests to banks within any one of the first and second memory portions is longer than a time between consecutive access requests to banks within different ones of the first and second memory portions;
- and
- a port to send the access requests from the controller to the DRAM.
A method of operation in a controller, wherein the controller operates a dynamic random access memory (DRAM) having at least first and second memory portions, wherein each of the first and second memory portions includes a plurality of memory banks, the method comprising:
- sending to the DRAM, a plurality of indications for which memory portion, of the first and second memory portions, to be selected for consecutive accesses;
- and
- for each of the consecutive accesses to the first and second memory portions, timing access requests to the first and second portions of the DRAM such that a delay time between consecutive access requests to banks within any one of the first and second memory portions is longer than a time between any access request to a bank within the first memory portion followed by an access request to a bank within the second memory portion.
A controller to control the operation of a dynamic random access memory (DRAM) having at least first and second memory portions, wherein each of the first and second memory portions includes
- a plurality of memory banks, the controller comprising:
- means for controlling the timing of access requests to the first and second portions of the DRAM such that a delay time between consecutive access requests to banks within any one of the first and second memory portions is longer than a time between any access request to a bank within the first memory portion followed by an access request to a bank within the second memory portion;
- and
- means for sending the access requests to the DRAM, the access request including an indication to the DRAM of which of the first and second memory portions is selected for the access.
Dependencies are inferred from the claim text.