Method And Apparatus For A Zero Voltage Processor Sleep State

A mobile system comprising:

• an operating system;
• a battery;
• a wireless communication module;
• and
• a multi-core processor to include a first processor core and a second processor core;
• the first processor core to save a state of the first processor core in a memory and to enter a mode in which the first processor core is powered off;
• the second processor core to save a state of the second processor core in a memory and to enter a mode in which the second processor core is powered off;
• and
• cache memory of the processor, the cache memory to remain powered when the first processor core is powered off;
• the first processor core to restore the saved state of the first processor core in response to the first processor core entering a mode in which the first processor core is powered;
• the second processor core to restore the saved state of the second processor core in response to the second processor core entering a mode in which the second processor core is powered;
• and
• wherein the state of the first processor is to include architectural state information associated with the first processor and the state of the second processor is to include architectural state information associated with the second processor.

A system comprising:

• a graphics circuitry;
• a wireless communication block;
• a multi-core processor to include a first processor core and a second processor core;
• the first processor core to save a state of the first processor core in a memory and to enter a mode in which the first processor core is powered off;
• the second processor core to save a state of the second processor core in a memory and to enter a mode in which the second processor core is powered off;
• and
• cache memory of the processor, the cache memory to remain powered when the first processor core is powered off;
• the first processor core to restore the saved state of the first processor core in response to the first processor core entering a mode in which the first processor core is powered;
• the second processor core to restore the saved state of the second processor core in response to the second processor core entering a mode in which the second processor core is powered;
• and
• wherein the state of the first processor is to include architectural state information associated with the first processor and the state of the second processor is to include architectural state information associated with the second processor.

An processor comprising:

• a first core to execute sequences of instructions;
• a second core to execute sequences of instructions;
• a shared cache accessible by both the first core and the second core;
• power management logic to cause the first core to be powered down while the second core remains in an active state, to maintain power to the shared cache to be accessed by the second core and to preserve data associate with the first core when the first core is powered down;
• and
• an execution unit to execute at least one instruction to reduce consumption of the processor to enter into a low power state.