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US 2016/0098073 A1Published application
Clock-free dual-data-rate link with built-in flow control
AssigneeQUALCOMM Incorporated
InventorsLalan Jee Mishra, Richard Wietfeldt, James Panian
Life of this patent
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Abstract
A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.
Claims22
A dual-data-rate interface for an integrated circuit, comprising:
- a transmit pin;
- a first memory configured to store first fetch clock transitions received on the transmit pin, wherein the first fetch clock transitions correspond to a plurality of first data bits, and wherein the first memory is further configured to store each first fetch clock transition as a binary state;
- and
- a first timing and control circuit configured to drive each first data bit over the transmit pin responsive to a receipt on the transmit pin of the corresponding first fetch clock transition, wherein the first timing and control circuit is further configured to restore a voltage for the transmit pin responsive to the binary state stored in the memory for the corresponding first fetch clock transition.
1 more element
A method of communication, comprising:
- driving a current edge of a fetch clock to a transmitter by driving a bus coupling a receiver to the transmitter into a current binary voltage state that is a complement of a previous binary voltage state for the bus used for a previous edge of the fetch clock;
- in the receiver, receiving a current data bit from the transmitter over the bus after driving the current edge of the fetch clock and before driving a subsequent edge of the fetch clock;
- driving the subsequent edge of the fetch clock to the transmitter by driving the bus into a subsequent binary voltage state that is a complement of the current binary voltage state;
- and
- in the receiver, receiving a subsequent data bit from the transmitter over the bus after driving the subsequent edge of the fetch clock.
2 more elements
A method of communication, comprising:
- for a series of binary transitions of a bus voltage for a bus coupling a transmit pin on a transmitter to a receive pin on a receiver, transmitting a successive bit in a series of bits over the transmit pin to the receive pin responsive to detecting each binary transition of the bus voltage in the series;
- and
- after each bit transmission, restoring the bus voltage to a binary state for a preceding one of the binary transitions of the bus voltage.
An integrated circuit, comprising:
- a transmit pin;
- a memory configured to store fetch clock transitions received on the transmit pin, wherein the fetch clock transitions correspond to a plurality of data bits, and wherein the memory is further configured to store each fetch clock transition as a binary state;
- and
- means for shifting out successive bits of a data frame responsive to receiving successive ones of the fetch clock transitions over the transmit pin and for restoring a binary voltage state for the transmit pin after each successive bit transmission responsive to the binary state for a preceding fetch clock transition retrieved from the memory.
1 more element
Dependencies are inferred from the claim text.