Voltage droop reduction in a processor

A method for managing a processor, the processor comprising a common supply rail and one or more processor cores being connected to the common supply rail, the method comprising:

• generating for each processor core a dynamic instructions per cycle (dIPC) value indicative of an activity level of the respective processor core;
• deriving a current global dIPC value from the dIPC values of the one or more processor cores;
• calculating an absolute difference of the current global dIPC value and an average global historic dIPC value;
• comparing the absolute difference of the current global dIPC value and the average global historic dIPC value with a threshold global dIPC value;
• and
• triggering a threshold signal if the absolute difference of the current global dIPC value and the average global historic dIPC value is above the threshold global dIPC value.

A computer program product for managing a processor, the processor comprising a common supply rail and one or more processor cores connected to the common supply rail, the computer program product comprising:

• a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to perform a method, the method comprising:
• generating for each processor core a dynamic instructions per cycle (dIPC) value indicative of an activity level of the respective processor core;
• deriving a current global dIPC value from the dIPC values of the one or more processor cores;
• calculating an absolute difference of the current global dIPC value and an average global historic dIPC value;
• comparing the absolute difference of the current global dIPC value and the average global historic dIPC value with a threshold global dIPC value;
• and
• triggering a threshold signal if the absolute difference of the current global dIPC value and the average global historic dIPC value is above the threshold global dIPC value.