Timing control with body-bias
AssigneeNXP B.V.
InventorsVibhu Sharma, Ajay Kapoor, Ralf Malzahn
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Abstract
Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.
Claims20
An apparatus comprising:
- a plurality of circuits operating in respective clock domains, each circuit including a semiconductor body region via which at least one clock signal path traverses;
- a clock circuit configured and arranged to generate and provide respective clock signals for each clock domain;
- a plurality of timing sensors including, for at least one of the circuits in each clock domain, a timing sensor configured and arranged to detect timing characteristics of the at least one clock signal path;
- and
- a plurality of local bias circuits including, for the semiconductor body region in at least one of the circuits in each clock domain, a bias circuit coupled to the semiconductor body region and configured and arranged to bias the semiconductor body region at a bias level that is based on the detected timing characteristics of the at least one clock signal path that traverses the semiconductor body region.
A method comprising:
- for a plurality of circuits operating in respective clock domains, each circuit including a semiconductor body region via which at least one clock signal path traverses, generating and providing respective clock signals for each clock domain;
- detecting timing characteristics of the at least one clock signal path in at least one of the circuits in each clock domain, using a timing sensor for each clock signal path;
- and
- for each of the semiconductor body regions, biasing the semiconductor body region with a local bias circuit at a bias level that is based on the detected timing characteristics of the at least one clock signal path that traverses the semiconductor body region.
An apparatus comprising:
- a sensor circuit configured and arranged to detect timing characteristics of circuitry operating in respective clock domains, each circuit including a semiconductor body region via which at least one clock signal path traverses;
- and
- a bias circuit configured and arranged to bias the respective semiconductor body regions at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.
Dependencies are inferred from the claim text.