Scalable 2.5d interface architecture
AssigneeAltera Corporation
InventorChee Hak Teh
Life of this patent
Estimating the term…
Abstract
Systems and methods for interface block. The interface block includes input/output modules distributed along the interface block and a mid-stack module interspersed within the input/output modules. The input/output modules include at least one data module and at least one command module. At least one of the input/output modules is shared by an adjacent pair of channels. Each of the input/output modules is configured to interface with a memory device via a silicon interposer or equivalent. The mid-stack module is in communication with the input/output modules via programmable logic circuitry. The mid-stack module may include independent clock quadrants. Each clock quadrant is configured to operate at different phases where each phase is aligned to a respective core clock.
Claims21
An interface block comprising:
- a plurality of input/output modules distributed along the interface block;
- and
- a mid-stack module interspersed within the plurality of input/output modules, the mid-stack module in communication with the plurality of input/output modules via programmable logic circuitry,
- wherein:
- the plurality of input/output modules comprises at least one data module and at least one command module,
- at least one of the plurality of input/output modules is shared by an adjacent pair of channels, and
- each of the plurality of input/output modules is configured to interface with a memory device via one of a silicon interposer and a silicon bridge.
An interface block comprising:
- a plurality of input/output modules distributed along the interface block, wherein the plurality of input/output modules comprises at least one data module and at least one command module, wherein at least one of the plurality of input/output modules is shared by an adjacent pair of channels, and wherein each of the plurality of input/output modules is configured to interface with a memory device via one of a silicon interposer and a silicon bridge.
An interface block comprising:
- a plurality of input/output modules distributed along the interface block;
- and
- a mid-stack module interspersed within the plurality of input/output modules, the mid-stack module in communication with the plurality of input/output modules via programmable logic circuitry, wherein the mid-stack module comprises independent clock quadrants, wherein each clock quadrant is configured to operate at different phases, and wherein each phase is aligned to a respective core clock.
Dependencies are inferred from the claim text.