Process for fabricating an integrated circuit comprising at least one coplanar waveguide
AssigneeSTMicroelectronics S.r.l.
InventorsSylvain Joblot, Pierre Bar
Life of this patent
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Abstract
An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
Claims20
A method, comprising:
- producing at least one through-silicon via (TSV) through a semiconductor support;
- producing at least one coplanar waveguide (CPW) above the semiconductor support;
- wherein producing said at least one through-via comprises producing at least one through-cavity through the semiconductor support;
- and
- after the waveguide has been produced, forming a trench under the waveguide and extending over at least an entire length of the waveguide;
- wherein said at least one cavity and said at least one trench are produced simultaneously and have substantially a same depth.
A method, comprising:
- forming a coplanar waveguide over a top side of a support, said coplanar waveguide comprising an electrically conductive line separated from and placed between two ground lines;
- forming a through silicon via in a back side of the support;
- and
- forming a first trench and second trench in the back side of the support, said first and second trenches extending along a length of the coplanar waveguide, and said first and second trenches being located underneath separating regions said support which separate each ground line from the electrically conductive line.
A method, comprising:
- producing at least one coplanar waveguide in a metallization layer above a semiconductor support, said coplanar waveguide comprising an electrically conductive line separated from and placed between two ground lines;
- and
- forming a first trench in the semiconductor support at a location under the coplanar waveguide, between the electrically conductive line and one of said ground lines and extending along a length of the coplanar waveguide;
- and
- forming a second trench in the semiconductor support at a location under the coplanar waveguide, between the electrically conductive line and another one of said ground lines and extending along the length of the coplanar waveguide;
- wherein the first trench and second trench have substantially a same depth.
Dependencies are inferred from the claim text.