# US 2016/0092779 A1 · Implementations of, and methods of use for a pattern memory engine applying associative pattern memory for pattern recognition

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- Number: US 2016/0092779 A1
- Document ID: US20160092779A1
- Status: Published application
- Kind: A1
- Application number: 14/870,990
- Filed: 2015-09-30
- Published: 2016-03-31
- Earliest claimed: 2014-09-30
- Assignees: BoonLogic
- Applicants: BoonLogic
- Inventors: Larry Werth
- Web page: https://patentgrep.com/patent/US20160092779A1

## CPC

- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 18/2414: {Smoothing the distance, e.g. radial basis function networks [RBFN]}
- G06N 3/044: Recurrent networks, e.g. Hopfield networks
- G06N 3/0442: characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
- G06N 3/09: Supervised learning
- G06N 20/00: Machine learning
- G06N 20/10: using kernel methods, e.g. support vector machines [SVM]
- G06N 20/20: Ensemble learning
- G06V 10/764: using classification, e.g. of video objects
- G06V 10/955: {using specific electronic processors}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING

## Abstract

Computer-readable storage memory may include a) input memory having addressable blocks of random access memory storing an input data pattern, b) pattern input address memory having addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory, c) current state address memory comprising a block of random access memory storing a current state address, and d) at least one next state memory having addressable blocks of random access memory, each of the addressable blocks storing predetermined data determining a next state address. The pattern input address memory and the at least one next state memory may each be sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory. The current state address may index an addressable block of the pattern input address memory and the at least one next state memory.

## Claims

### Claim 1

A computer-readable storage memory comprising:
input memory comprising addressable blocks of random access memory, the input memory storing an input data pattern;
pattern input address memory comprising addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory;
current state address memory comprising a block of random access memory storing a current state address; and
at least one next state memory comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory;
wherein the pattern input address memory and the at least one next state memory are each sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory; and
wherein the current state address indexes an addressable block of the pattern input address memory and the at least one next state memory.

### Claim 2 (depends on 1)

The computer-readable storage memory of claim 1,
wherein the at least one next state memory comprises at least two next state memories, each comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; and
wherein data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address determines which of the at least two next state memories to index for determining a next state address to store in the current state address memory.

### Claim 3 (depends on 2)

The computer-readable storage memory of claim 2, further comprising:
magnitude comparison memory comprising addressable blocks of random access memory, each of the addressable blocks storing a predetermined magnitude value;
wherein data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address is compared with a magnitude value in an addressable block of the magnitude comparison memory indexed by the current state address, and the result of the comparison determines which of the at least two next state memories to index for determining a next state address to store in the current state address memory.

### Claim 4 (depends on 1)

The computer-readable storage memory of claim 1, wherein the predetermined data in each of the addressable blocks of the at least one next state memory comprises a random number between a predetermined range of numbers.

### Claim 5 (depends on 1)

The computer-readable storage memory of claim 1, wherein the predetermined data in each of the addressable blocks of the at least one next state memory comprises a next state address value, the next state address value being a summation of an index of the respective addressable block of the at least one next state memory and a random number between a predetermined range of numbers.

### Claim 6 (depends on 2)

The computer-readable storage memory of claim 2, further comprising ID memory comprising addressable blocks of random access memory, each of the addressable blocks storing an ID hash of predetermined bits, and addressable by an ID hash index.

### Claim 7 (depends on 6)

The computer-readable storage memory of claim 6, further comprising vertical sensory memory comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data from which a hash index and bit number can be determined, the bit number identifying which bit in the ID hash indexed in the ID memory by the hash index to set.

### Claim 8 (depends on 1)

The computer-readable storage memory of claim 1, further comprising:
pattern map memory comprising addressable blocks of random access memory, data in an addressable block of the pattern map memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address;
wherein each addressable block of the pattern map memory stores data identifying the type of data stored in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address.

### Claim 9 (depends on 8)

The computer-readable storage memory of claim 8, wherein the type of data stored in an addressable block of the input memory comprises one of binary data, magnitude data, or category data.

### Claim 10 (depends on 9)

The computer-readable storage memory of claim 9, wherein category data comprises data from a dataset having a predetermined number of data choices.

### Claim 11 (depends on 10)

The computer-readable storage memory of claim 10,
wherein the at least one next state memory comprises a next state memory corresponding to each data choice, each comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; and
wherein, if an addressable block of the pattern map memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address identifies the type of data stored in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address as a category type, then a next state address to store in the current state address memory is determined from data in the next state memory corresponding to the data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address.

### Claim 12 (depends on 6)

The computer-readable storage memory of claim 6, wherein the ID hashes of ID memory are determined from a sequence of selections of the at least two next state memories.

### Claim 13 (depends on 1)

A parallel pattern memory engine comprising at least two of the computer-readable storage memories of claim 1 operating in parallel.

### Claim 14 (depends on 13)

The parallel pattern memory engine of claim 13,
wherein the addressable blocks of the pattern input address memory of one of the at least two of the computer-readable storage memories comprises a different set of predetermined addresses than the addressable blocks of the pattern input address memory of another of the at least two of the computer-readable storage memories; and
wherein the addressable blocks of the at least one next state memory of one of the at least two of the computer-readable storage memories comprises a different set of predetermined data than the addressable blocks of the at least one next state memory of another of the at least two of the computer-readable storage memories.

### Claim 15 (depends on 13)

The parallel pattern memory engine of claim 13, wherein the input data pattern of one of the at least two of the computer-readable storage memories comprises data from a different source than the input data pattern of another of the at least two of the computer-readable storage memories.

### Claim 16 (depends on 15)

The parallel pattern memory engine of claim 15, further comprising:
a first sensor generating a first type of data and providing pattern data as the input data pattern to one of the at least two of the computer-readable storage memories; and
a second sensor generating a second type of data and providing pattern data as the input data pattern to another of the at least two of the computer-readable storage memories.

### Claim 17 (depends on 1)

A serial pattern memory engine comprising at least two of the computer-readable storage memories of claim 1 operating in serial, such that a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a lower level provides its output to a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a higher level.

### Claim 18 (depends on 1, 17)

The serial pattern memory engine of claim 17, further comprising at least two of the computer-readable storage memories of claim 1 operating in parallel.

### Claim 19 (depends on 1, 17)

The serial pattern memory engine of claim 17, wherein a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a higher level provides its output as feedback to a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a lower level.