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US 2016/0081201 A1Published application
Multilayer electronic structure with integral faraday shielding
AssigneeZhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
InventorDror Hurwitz
Life of this patent
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Abstract
A multilayer electronic support structure including at least one metallic component encapsulated in a dielectric material, and comprising at least one faraday barrier to shield the at least one metallic component from interference from external electromagnetic fields and to prevent electromagnetic emission from the metallic component.
Claims19
A method of fabricating a multilayer electronic structure, comprising the steps of:
- (a) Obtaining a substrate including an upper layer comprising a continuous metal ground plane;
- (b) Applying a first layer of photoresist over the continuous metal ground plane;
- (c) Developing the first layer of photoresist with a pattern comprising a pair of lower rows of metal vias;
- (d) Pattern plating the pair of lower rows of metal vias into the first layer of photoresist;
- (e) Stripping away the first layer of photoresist;
- (f) Laminating a first layer of dielectric material over the pair of lower rows of metal vias;
- (g) Thin away the first layer of dielectric material to expose ends of the pair of lower rows of metal vias;
- (h) Deposit a first metal seed layer over the first layer of dielectric material;
- (i) Apply a second layer of photoresist over the first metal seed layer;
- (j) Expose and develop a pattern including a metallic element, adjacent faraday barriers on both sides in the second layer of photoresist and conductive pads aligned with the lower rows of metal vias;
- (k) Cofabricate the metallic element, adjacent faraday barriers and conductive pad by pattern plating by electroplating pure copper into the pattern;
- (l) Strip away the second layer of photoresist;
- (m) Apply a third layer of photoresist;
- (n) Expose and develop a third pattern comprising upper rows of via posts in the third layer of photoresist aligned with the conductive pads;
- (o) Pattern plate the upper rows of via posts into the exposed and developed pattern;
- (p) Strip away the third layer of photoresist;
- (q) Remove the seed layer;
- (r) Laminate a layer of dielectric material over the upper rows of via posts;
- (s) Thin away the dielectric material expose ends of the upper rows of via posts, and
- (t) Deposit an upper layer of metal over the exposed ends.
17 more elements
A method of fabricating a multilayer electronic structure, comprising the steps of:
- providing a lower metal layer having a surface;
- forming on the surface of the lower metal layer a second layer, including the steps of
- depositing a first amount photoresist,
- patterning into the first amount of photoresist a lower set of vias,
- electroplating the lower set of vias,
- applying dielectric whereby the ends of the lower set of vias are exposed;
- forming on the second layer a third layer having a first and second pad separated from at least one functional metallic component by dielectric;
- forming on the third layer a fourth layer, including the steps of depositing a second amount photoresist,
- patterning into the second amount of photoresist an upper set of vias,
- electroplating the upper set of vias,
- applying dielectric whereby the ends of the upper set of vias are exposed;
- and
- depositing an upper metal layer on the fourth layer.
10 more elements
Dependencies are inferred from the claim text.