Phase detecting device and clock data recovery circuit embedded with decision feedback equalizer

A clock data recovery circuit, comprising:

• a phase detecting device including:
• a decision feedback equalizer including a first feedback equalization circuit having a first sample-hold sub-circuit and a second feedback equalization circuit having a second sample-hold sub-circuit, wherein the first sample-hold sub-circuit obtains first sample data of an input data signal in light of a positive clock signal, and the second sample-hold sub-circuit obtains second sample data of the input data signal in light of a negative clock signal corresponding to the positive clock signal;
• an edge detector electrically connected to the first feedback equalization circuit and the second feedback equalization circuit and having a third sample-hold sub-circuit that obtains transition data of the input data signal in light of an edge clock signal corresponding to the positive clock signal;
• a first XOR gate electrically connected to the first feedback equalization circuit and the edge detector and executing an XOR operation for the first sample data and the transition data to generate first clock phase shift information;
• and
• a second XOR gate electrically connected to the second feedback equalization circuit and the edge detector and executing the XOR operation for the second sample data and the transition data to generate second clock phase shift information;
• and
• a clock adjustment circuit electrically connected to the phase detecting device and adjusting phases of the positive clock signal, the negative clock signal and the edge clock signal based on the first clock phase shift information and the second clock phase shift information.