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US 2016/0080139 A1Published application
Receivers and semiconductor systems including the same
AssigneeSK hynix Inc.
InventorKeun Soo SONG
Life of this patent
Estimating the term…
Abstract
The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.
Claims9
A semiconductor system comprising:
- a transmitter configured to generate a first internal clock signal, a second internal clock signal, and a data;
- and
- a receiver configured to retard the first and second internal clock signals to generate a first delayed internal clock signal and a second delayed internal clock signal, configured to buffer the data in synchronization with the first and second internal clock signals, and configured to buffer the buffered data in synchronization with the first and second delayed internal clock signals to generate a first input data and a second input data.
Dependencies are inferred from the claim text.