Integrated control module for communication system on a chip for silicon photonics

An integrated multi-chip device, the device comprising:

• a first silicon substrate member;
• a second silicon substrate member;
• a third silicon substrate member;
• a data input/output interface provided on the first silicon substrate member and configured for a predefined data rate and protocol;
• an input/output block provided on the first silicon substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a signal processing block provided on the first silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol;
• a driver module provided on the second silicon substrate member and coupled to the signal processing block using a uni-directional multi-lane bus through PCB traces;
• a driver interface coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data an amplitude modulation format;
• a receiver module comprising a TIA block provided on the third silicon substrate member and to be coupled to the silicon photonics device using predefined modulation format, and coupled to the signal processing block using a uni-directional multi-lane bus through PCB traces to communicate information to the input/output block for transmission through the data input/output interface;
• a laser device coupled to the silicon photonics device;
• a communication block provided on the first silicon substrate member and directly coupled to the input/output block, the signal processing block, and operably coupled to the driver module and the receiver module;
• a communication interface coupled to the communication block;
• and
• a control block provided on the first silicon substrate member and coupled to the communication block, the control block being configured to receive and send instruction(s) in a digital format to the communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the communication interface;
• and
• wherein the amplified modulation format is a PAM format.

An integrated multi-chip device, the device comprising:

• a first silicon substrate member;
• a second silicon substrate member;
• a data input/output interface provided on the first silicon substrate member and configured for a predefined data rate and protocol;
• an input/output block provided on the first silicon substrate member and coupled to the data input/output interface, the input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a signal processing block provided on the first silicon substrate member and coupled to the input/output block using a bi-direction bus in an intermediary protocol;
• a driver module provided on the second silicon substrate member and coupled to the signal processing block using a uni-directional multi-lane bus through PCB traces;
• a driver interface coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in an amplitude modulation format, the amplitude modulation formation being a PAM format;
• a receiver module comprising a TIA block provided on the first silicon substrate member and to be coupled to the silicon photonics device using predefined modulation format, and coupled to the signal processing block to communicate information to the input/output block for transmission through the data input/output interface;
• a laser diode device is coupled of the silicon photonics device;
• a communication block provided on the first silicon substrate member and directly coupled to the input/output block, the signal processing block, and operably coupled to the driver module through PCB trances and to the receiver module using a uni-directional multi-lane bus;
• a communication interface coupled to the communication block;
• a control block provided on the first silicon substrate member and coupled to the communication block, the control block being configured to receive and send instruction(s) in a digital format to the communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the communication interface.

An integrated multi-chip device, the device comprising:

• a first silicon substrate member;
• a second silicon substrate member;
• a first data input/output interface provided on the first silicon substrate member and configured for a predefined data rate and protocol;
• a first input/output block provided on the first silicon substrate member and coupled to the first data input/output interface, the first input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a first signal processing block provided on the first silicon substrate member and coupled to the first input/output block using a bi-direction bus in an intermediary protocol;
• a receiver module comprising a TIA block provided on the first silicon substrate member and to be coupled to a silicon photonics device using predefined modulation format, and coupled to the first signal processing block using a uni-directional bus on the first silicon substrate member to communicate information to the first input/output block for transmission through the first data input/output interface;
• a first communication block provided on the first silicon substrate member and directly coupled to the first input/output block, the first signal processing block, and operably coupled to the receiver module;
• a first communication interface coupled to the first communication block;
• a first control block provided on the first silicon substrate member and coupled to the first communication block, the first control block being configured to receive and send instruction(s) in a digital format to the first communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the first communication interface;
• a second data input/output interface provided on the second silicon substrate member and configured for a predefined data rate and protocol;
• a second input/output block provided on the second silicon substrate member and coupled to the second data input/output interface, the second input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a second signal processing block provided on the second silicon substrate member and coupled to the second input/output block using a bi-direction bus in an intermediary protocol;
• a driver module provided on the second silicon substrate member and coupled to the second signal processing block using a uni-directional multi-lane bus on the second silicon substrate;
• a driver interface coupled to the driver module and configured to be coupled to a silicon photonics device, the driver interface being configured to transmit output data in an amplitude modulation format, the amplitude modulation formation being a PAM format;
• a laser device being coupled to the silicon photonics device;
• a second communication block provided on the second silicon substrate member and directly coupled to the second input/output block, the second signal processing block, and operably coupled to the driver module;
• a second communication interface coupled to the second communication block;
• and
• a second control block provided on the second silicon substrate member and coupled to the second communication block, the second control block being configured to receive and send instruction(s) in a digital format to the second communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the second communication interface.

An integrated multi-chip device, the device comprising:

• a first silicon substrate member;
• a second silicon substrate member;
• a third silicon substrate member;
• a fourth silicon substrate member;
• a first data input/output interface provided on the first silicon substrate member and configured for a predefined data rate and protocol;
• a first input/output block provided on the first silicon substrate member and coupled to the first data input/output interface, the first input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a first signal processing block provided on the first silicon substrate member and coupled to the first input/output block using a bi-direction bus in an intermediary protocol;
• a driver module provided on the third silicon substrate member and coupled to the first signal processing block using a uni-directional multi-lane bus through PCB traces;
• a driver interface coupled to the driver module and configured to be coupled to a silicon photonics device and to transmit output data in an amplitude modulation format, the amplitude modulation formation being a PAM format;
• a first communication block provided on the first silicon substrate member and directly coupled to the first input/output block, the first signal processing block, and operably coupled to the driver module;
• a first communication interface coupled to the first communication block;
• a first control block provided on the first silicon substrate member and coupled to the first communication block, the first control block being configured to receive and send instruction(s) in a digital format to the first communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the first communication interface;
• a second data input/output interface provided on the second silicon substrate member and configured for a predefined data rate and protocol;
• a second input/output block provided on the second silicon substrate member and coupled to the second data input/output interface, the second input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a second signal processing block provided on the second silicon substrate member and coupled to the second input/output block using a bi-direction bus in an intermediary protocol;
• a receiver module comprising a TIA block provided on the fourth silicon substrate member and to be coupled to the silicon photonics device using predefined modulation format, and coupled to the second signal processing block using a uni-directional multi-lane bus through PCB traces to communicate information to the second input/output block for transmission through the second data input/output interface;
• a second communication block provided on the second silicon substrate member and directly coupled to the second input/output block, the second signal processing block, and operably coupled to the receiver module;
• a second communication interface coupled to the second communication block;
• and
• a second control block provided on the second silicon substrate member and coupled to the second communication block, the second control block being configured to receive and send instruction(s) in a digital format to the second communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the second communication interface.

An integrated multi-chip device, the device comprising:

• a first silicon substrate member;
• a second silicon substrate member;
• a third silicon substrate member;
• a first data input/output interface provided on the first silicon substrate member and configured for a predefined data rate and protocol;
• a first input/output block provided on the first silicon substrate member and coupled to the first data input/output interface, the first input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a first signal processing block provided on the first silicon substrate member and coupled to the first input/output block using a bi-direction bus in an intermediary protocol;
• a driver module provided on the third silicon substrate member and coupled to the first signal processing block using a uni-directional multi-lane bus through PCB traces;
• a driver interface coupled to the driver module and configured to be coupled to a silicon photonics device and to transmit output data in either an amplitude modulation format, the amplitude modulation formation is a PAM format;
• a first communication block provided on the first silicon substrate member and directly coupled to the first input/output block, the first signal processing block, and operably coupled to the driver module;
• a first communication interface coupled to the first communication block;
• a first control block provided on the first silicon substrate member and coupled to the first communication block, the first control block being configured to receive and send instruction(s) in a digital format to the first communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the first communication interface;
• a second data input/output interface provided on the second silicon substrate member and configured for a predefined data rate and protocol;
• a second input/output block provided on the second silicon substrate member and coupled to the second data input/output interface, the second input/output block comprising a SerDes block, a CDR block, a compensation block, and an equalizer block;
• a second signal processing block provided on the second silicon substrate member and coupled to the second input/output block using a bi-direction bus in an intermediary protocol;
• a receiver module comprising a TIA block provided on the second silicon substrate member and to be coupled to the silicon photonics device using predefined modulation format, and coupled to the second signal processing block using a uni-directional multi-lane bus on the second silicon substrate member to communicate information to the second input/output block for transmission through the second data input/output interface;
• a second communication block provided on the second silicon substrate member and directly coupled to the second input/output block, the second signal processing block, and operably coupled to the receiver module;
• a second communication interface coupled to the second communication block;
• and
• a second control block provided on the second silicon substrate member and coupled to the second communication block, the second control block being configured to receive and send instruction(s) in a digital format to the second communication block and being configured to receive and send signals in an analog format to communicate with the silicon photonics device via the second communication interface.