Lane-to-lane de-skew for transmitters
AssigneeXilinx, Inc.
InventorsPaolo Novellini, Giovanni Guasti
Life of this patent
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Abstract
In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.
Claims20
A method for starting a plurality of transmitters, comprising:
- initiating a sequence for each of the plurality of transmitters having corresponding data buffers;
- and
- setting latency for each of the data buffers responsive to execution of the sequence;
- wherein the sequence comprises:
- obtaining a read address associated with a read clock signal;
- obtaining a write address associated with a write clock signal;
- determining a difference between the read address and the write address;
- asserting a flag signal associated with the difference;
- and
- adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.
A method for starting a plurality of transmitters, comprising:
- initiating a sequence for each of the plurality of transmitters having corresponding data buffers;
- and
- setting latency for each of the data buffers responsive to execution of the sequence;
- wherein the sequence comprises:
- obtaining a read address associated with a read clock signal;
- obtaining a write address associated with a write clock signal;
- determining a difference between the read address and the write address;
- asserting a flag signal associated with the difference;
- adjusting the read clock signal to change the difference;
- and
- repeating the steps of the sequence to locate a change of state location of the flag signal;
- wherein the change of state location is for a domain crossing between a read time domain of the read clock signal and a write time domain of the write clock signal;
- and
- wherein the latency for a data buffer of the data buffers is set to the change of state location.
An integrated circuit device having a plurality of transmitters, comprising:
- a first transmitter of the plurality of transmitters including a first data buffer and a first input/output control block coupled to the first data buffer;
- and
- a second transmitter of the plurality of transmitters including a second data buffer and a second input/output control block coupled to the second data buffer;
- wherein the first data buffer has a first delay;
- wherein the second data buffer has a second delay;
- wherein the first input/output control block is:
- coupled to receive a write clock signal and a first read clock signal and configured to generate a first write address and a first read address respectively therefor;
- configured to determine a first difference between the first write address and the first read address and to assert a first flag signal associated with the first difference;
- and
- coupled to feedback the first flag signal to adjust the first read clock signal to adjust the first difference to reach a first change of state location for the first flag signal associated with a first position in the first data buffer;
- and
- wherein the second input/output control block is:
- coupled to receive the write clock signal and a second read clock signal and configured to generate a second write address and a second read address respectively therefor;
- configured to determine a second difference between the second write address and the second read address and to assert a second flag signal associated with the second difference;
- and
- coupled to feedback the second flag signal to adjust the second read clock signal to adjust the second difference to reach a second change of state location for the second flag signal associated with a second position in the second data buffer.
Dependencies are inferred from the claim text.