Phase error detection in phase lock loop and delay lock loop devices
AssigneeInternational Business Machines Corporation
InventorsJohn W. STANTON, Pradeep THIAGARAJAN
Life of this patent
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Abstract
A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
Claims11
A method of lock detection comprising, using an analog circuit to:
- convert a reference clock to a reference triangle wave;
- convert a feedback clock to a feedback triangle wave;
- determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave;
- and
- generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
Dependencies are inferred from the claim text.