Variable rate interpolation with numerically controlled oscillator
AssigneeEchoStar Technologies L.L.C.
InventorsSantharam Gurumani, Bala Subramaniam
Life of this patent
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Abstract
A numerically controlled oscillator includes a phase accumulator that outputs a phase word and a clock that periodically outputs a clock signal in accordance with a delay interval. The phase accumulator outputs a new phase word in response to receiving the clock signal. A clock controller calculates a timing drift and adjusts the delay interval to reduce the timing drift. A method includes receiving a plurality of frequency control words, calculating a delay interval, accumulating the frequency control words in accordance with the delay interval to generate a phase word, converting the phase word to a waveform, calculating a timing drift, and adjusting the delay interval to reduce the timing drift.
Claims20
A numerically controlled oscillator comprising:
- a phase accumulator configured to output a phase word;
- a clock configured to periodically output a variable clock signal in accordance with a delay interval, wherein the phase accumulator is configured to output a new phase word in response to receiving the clock signal;
- and
- a clock controller programmed to calculate a timing drift from a ratio of an output sample rate to an input sample rate and adjust a length of the delay interval of the variable clock signal to reduce the calculated timing drift, wherein a length of the delay interval of the variable clock signal is a function of the calculated timing drift.
(canceled)
A method comprising:
- receiving a plurality of frequency control words in accordance with a variable clock signal;
- calculating, via a clock controller, a delay interval of the variable clock signal;
- accumulating the frequency control words in accordance with the delay interval to generate a phase word;
- converting the phase word to a waveform;
- calculating a timing drift from a ratio of an output sample rate to an input sample rate;
- and
- adjusting a length of the delay interval of the variable clock signal to reduce the calculated timing drift, wherein the length of the delay interval is a function of a calculated timing drift.
(canceled)
A numerically controlled oscillator comprising:
- a phase accumulator having a digital input module configured to receive a plurality of control words, a summation block configured to output a phase word representing an accumulation of the plurality of frequency control words, and a delay block configured to provide the accumulation of the plurality of frequency control words to the summation block;
- a clock configured to periodically output a variable clock signal in accordance with a delay interval, wherein the phase accumulator is configured to output the accumulation of frequency control words in response to receiving the clock signal;
- and
- a clock controller programmed to calculate a timing drift from a ratio of an output sample rate to an input sample rate and adjust a length of the delay interval to reduce the calculated timing drift, wherein the length of the delay interval of the variable clock signal is a function of the calculated timing drift.
(canceled)
Dependencies are inferred from the claim text.