High-speed inverter and method thereof

A circuit comprising:

• a first CMOS (complementary metal oxide semiconductor) inverter comprising a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, and a first resistor, configured to receive a first signal and a second signal and output a third signal and a fourth signal, and
• a second CMOS inverter comprising a second PMOS transistor, a second NMOS transistor, and a second resistor, configured to receive the third signal and the fourth signal and output a fifth signal and a sixth signal, wherein:
• the first PMOS transistor inverts a high-to-low transition of the first signal into a low-to-high transition of the fourth signal;
• the first NMOS transistor inverts a low-to-high transition of the second signal into a high-to-low transition of the third signal;
• the first resistor provides an isolation between the third signal and the fourth signal;
• the second PMOS transistor inverts a high-to-low transition of the third signal into a low-to-high transition of the sixth signal;
• the second NMOS transistor inverts a low-to-high transition of the fourth signal into a high-to-low transition of the fifth signal;
• and
• the second resistor provides an isolation between the fifth signal and the sixth signal.

A circuit comprising:

• a first CMOS (complementary metal oxide semiconductor) inverter comprising a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, and a first resistor, configured to receive a first signal and a second signal and output a third signal and a fourth signal;
• and
• a second CMOS inverter comprising a second PMOS transistor, a second NMOS transistor, and a second resistor, configured to receive the third signal and the fourth signal and output the first signal and the second signal, wherein:
• the first PMOS transistor inverts a high-to-low transition of the first signal into a low-to-high transition of the fourth signal;
• the first NMOS transistor inverts a low-to-high transition of the second signal into a high-to-low transition of the third signal;
• the first resistor provides an isolation between the third signal and the fourth signal;
• the second PMOS transistor inverts a high-to-low transition of the third signal into a low-to-high transition of the second signal;
• the second NMOS transistor inverts a low-to-high transition of the fourth signal into a high-to-low transition of the first signal;
• and
• the second resistor provides an isolation between the first signal and the second signal.