Buffer circuit
AssigneeKabushiki Kaisha Toshiba
InventorsKatsue Kawakyu, Masaru Mizuta
Life of this patent
Estimating the term…
Abstract
A first logic inversion unit generates an input inversion signal and a buffer unit generates a signal having a same logic as that of the input inversion signal. The first logic inversion unit includes first and second MOS transistors. The first and second MOS transistors have conductivity types different from each other. The buffer unit includes third to sixth MOS transistors. The third and fourth MOS transistors are connected in cascade between a third reference potential and an output node of the buffer unit and have conductivity types different from each other. The fifth and sixth MOS transistors are connected in cascade between the output node of the buffer unit and a fourth reference potential and have conductivity types different from each other.
Claims17
A buffer circuit comprising:
- a first logic inversion unit to generate an input inversion signal having an inversion of a logic of an input signal;
- and
- a buffer unit to generate a signal identical to a logic of the input inversion signal, wherein
- the first logic inversion unit comprises
- a first MOS transistor connected between a first reference potential and an output node of the first logic inversion unit, and
- a second MOS transistor connected between the output node of the first logic inversion unit and a second reference potential and having a conductivity type different from a conductivity type of the first MOS transistor, and
- the buffer unit comprises
- a third MOS transistor and a fourth MOS transistor connected in cascade between a third reference potential and an output node of the buffer unit and having conductivity types different from each other, and
- a fifth MOS transistor and a sixth MOS transistor connected in cascade between the output node of the buffer unit and a fourth reference potential and having conductivity types different from each other.
A buffer circuit comprising:
- a first logic inversion unit to generate an input inversion signal having an inversion of a logic of an input signal, and
- a buffer unit to generate a signal identical to a logic of the input inversion signal, wherein
- the buffer unit comprises
- a first transistor and a second transistor connected in cascade between a first potential and an output node of the buffer unit and having conductivity types different from each other, and
- a third transistor and a fourth transistor connected in cascade between the output node of the buffer unit and a second potential and having conductivity types different from each other, and
- at least one of the first to fourth transistors is turned OFF when an intermediate potential between the first potential and the second potential is input to the buffer unit.
Dependencies are inferred from the claim text.