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US 2016/0079979 A1Published application
Pulsed level shift and inverter circuits for gan devices
AssigneeNavitas Semiconductor Limited
InventorsDaniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
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Abstract
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
Claims21
A level shift circuit comprising:
- a first inverter circuit comprising:
- a first input terminal;
- a first output terminal;
- a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground;
- and
- a first pull up device coupled between the drain of the first GaN-based enhancement-mode transistor and a power supply;
- and
- a second inverter circuit comprising:
- a second input terminal;
- a second output terminal;
- a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground;
- and
- a second pull up device coupled between the drain of the second GaN-based enhancement-mode transistor and the power supply,
- wherein the first pull up device comprises a third GaN-based transistor having a gate voltage which is different from a voltage at the first output terminal, and
- wherein the first, second, and third transistors are of the same conductivity type.
12 more elements
An electronic power conversion component comprising:
- a package base;
- one or more GaN-based dies secured to the package base and comprising:
- a first inverter circuit comprising:
- a first input terminal;
- a first output terminal;
- a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground;
- and
- a first pull up device coupled between the drain of the first GaN-based enhancement-mode transistor and a power supply;
- and
- a second inverter circuit comprising:
- a second input terminal;
- a second output terminal;
- a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground;
- and
- a second pull up device coupled between the drain of the second GaN-based enhancement-mode transistor and the power supply,
- wherein the first pull up device comprises a third GaN-based transistor having a gate voltage which is different from a voltage at the first output terminal, and
- wherein the first, second, and third transistors are of the same conductivity type.
14 more elements
A method of operating GaN-based level shift circuit, the method comprising:
- receiving one or more control signals;
- generating a first pulse, the first pulse operating a first inverter circuit configured to change a state of an output node, wherein the first pulse is generated based on one or more logic levels of the one or more control signals;
- and
- generating a second pulse, the second pulse operating a second inverter circuit configured to change a state of the output node, wherein the second pulse is generated in response to a logic level transition of the one or more control signals.
1 more element
A level shift circuit, comprising:
- a first inverter circuit comprising:
- a first input terminal;
- a first output terminal;
- a first GaN-based enhancement-mode transistor having a gate coupled to the first input terminal, a drain coupled to the first output terminal, and a source coupled to a ground;
- and
- a first pull up device coupled between the drain of the first GaN-based enhancement-mode transistor and a power supply;
- a second inverter circuit comprising:
- a second input terminal;
- a second output terminal;
- a second GaN-based enhancement-mode transistor having a gate coupled to the second input terminal, a drain coupled to the second output terminal, and a source coupled to the ground;
- and
- a second pull up device coupled between the drain of the second GaN-based enhancement-mode transistor and the power supply;
- and
- a driver circuit configured to receive one or more control signals and to apply a first signal to the first input terminal of the first inverter and a second signal to the second input terminal of the second inverter, wherein the first signal is generated based on one or more logic levels of the one or more control signals, and wherein the second signal is generated in response to a logic level transition of the one or more control signals.
11 more elements
Dependencies are inferred from the claim text.