US 2016/0079944 A1Published application

Precision, high voltage, low power differential input stage with static and dynamic gate protection

AssigneeXcelsem, LLC

InventorsGregory L Schaffer, Maarten Jeroen Fonderie

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Abstract

A precision, high voltage, low power differential input stage including static and dynamic gate protection is disclosed herein. The differential input stage incorporates the performance of low voltage transistors with the high voltage capability of high voltage transistors. The transistors may be MOSFETs or the like. In addition, gate protection is provided to protect against large DC voltages and AC voltage transitions. The differential input stage includes a pair of input circuits, such as positive and negative input circuits, each including a cascode combination of low and high voltage transistors. In each cascode stage, the low voltage transistor is fabricated with a gate threshold voltage that is as high or higher than that of the high voltage transistors. The low voltage, high threshold transistors in the cascode stages may be configured to match each other. Resistors and capacitors may be provided to protect against excessive input current and voltage.

Claims20

Dependent claims

A differential input stage, comprising:

a first input circuit, comprising:
a first transistor having a first current terminal coupled to a first source node, having a second current terminal coupled to a first cascode node, and having a control terminal coupled to a first internal input node;
a second transistor having a first current terminal coupled to said first cascode node, having a second current terminal coupled to a first external output node, and having a control terminal coupled to said first internal input node;
a third transistor having a first current terminal coupled to said first source node, having a second current terminal coupled to an intermediate node, and having a control terminal coupled to said first internal input node;
a first current source that sources a first bias current to said first source node;
and
a first resistor coupled between a first external input node and said first internal input node;
and
a second input circuit, comprising:
a fourth transistor having a first current terminal coupled to a second source node, having a second current terminal coupled to a second cascode node, and having a control terminal coupled to a second internal input node;
a fifth transistor having a first current terminal coupled to said second cascode node, having a second current terminal coupled to a second external output node, and having a control terminal coupled to said second internal input node;
a sixth transistor having a first current terminal coupled to said second source node, having a second current terminal coupled to said intermediate node, and having a control terminal coupled to said second internal input node;
a second current source that sources a second bias current to said second source node;
and
a second resistor coupled between a second external input node and said second internal input node.

12 more elements

An amplifying device, comprising:

a differential input comprising a positive input node and a negative input node;
first and second supply nodes;
and
a differential input stage coupled to said differential input, comprising:
a first transistor having a first current terminal coupled to a first cascode node, having a second current terminal coupled to a first output node, and having a control terminal coupled to a first internal input node;
a second transistor having a first current terminal coupled to a first source node, having a second current terminal coupled to an intermediate node, and having a control terminal coupled to said first internal input node;
a third transistor having a first current terminal coupled to a second source node, having a second current terminal coupled to said intermediate node, and having a control terminal coupled to a second internal input node;
a fourth transistor having a first current terminal coupled to a second cascode node, having a second current terminal coupled to a second output node, and having a control terminal coupled to said second internal input node;
a fifth transistor having a first current terminal coupled to said first source node, having a second current terminal coupled to said first cascode node, and having a control terminal coupled to said first internal input node;
a sixth transistor having a first current terminal coupled to said second source node, having a second current terminal coupled to said second cascode node, and having a control terminal coupled to said second internal input node;
a first current source coupled to said first supply node and that sources a first bias current to said first source node;
a second current source coupled to said first supply node and that sources a second bias current to said second source node;
a first resistor coupled between said positive input node and said first internal input node;
and
a second resistor coupled between said negative input node and said second internal input node.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/840,289Filed 31 Aug 2015
Priority: 15 Sep 2014
Published: 17 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03F 3/45179
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using MOSFET transistors as the active…
H03F 1/523
Circuit arrangements for protecting such amplifiers: for amplifiers using field-effect devices
H03F 3/45475
Characterised by the way of implementation of the active amplifying circuit in the differential amplifier: using IC blocks as the active…
H03F 3/45
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements: differential amplifiers