Signal amplifier having inverted topology in stacked common gate structure

A signal amplifier comprising:

• a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal;
• a second common gate-type amplifying unit connected between the first common gate-type amplifying unit and a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal;
• a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit;
• and
• an impedance matching unit impedance-matching a signal summed by the signal summing unit,
• wherein the first common gate-type amplifying unit and the second common gate-type amplifying unit are formed in a cascode structure in which the first common gate-type amplifying unit and the second common gate-type amplifying unit are stacked between the source voltage terminal and a ground terminal, and
• the first common gate-type amplifying unit and the second common gate-type amplifying unit have levels of transconductance which are set so that matching of input impedance is undertaken.

A signal amplifier comprising:

• a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal;
• a second common gate-type amplifying unit connected between the first common gate-type amplifying unit and a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal;
• a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit;
• and
• an impedance matching unit impedance-matching a signal summed by the signal summing unit,
• wherein the first common gate-type amplifying unit and the second common gate-type amplifying unit form a single current path between the source voltage terminal and a ground terminal,
• the first common gate-type amplifying unit includes:
• a first NMOS transistor amplifying the input signal and providing the first signal to the signal summing unit;
• and
• a first PMOS transistor amplifying the input signal and providing the second signal to the signal summing unit,
• the second common gate-type amplifying unit includes:
• a second NMOS transistor amplifying the input signal and providing the third signal to the signal summing unit;
• and
• a second PMOS transistor amplifying the input signal and providing the fourth signal to the signal summing unit,
• the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and the second PMOS transistor are formed in a cascode structure in which the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and the second PMOS transistor are stacked between the source voltage terminal and the ground terminal, and
• the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and the second PMOS transistor have levels of transconductance which are set so that matching of input impedance is undertaken.

A signal amplifier comprising:

• a first common gate-type amplifying unit connected to a source voltage terminal, dividing an input signal into two signals, amplifying the two divided signals, respectively, and providing a first signal and a second signal;
• a second common gate-type amplifying unit connected between the first common gate-type amplifying unit and a ground, dividing the input signal into two signals, amplifying the two divided signals, respectively, and providing a third signal and a fourth signal;
• a signal summing unit summing the first signal and the second signal from the first common gate-type amplifying unit and the third signal and the fourth signal from the second common gate-type amplifying unit;
• and
• an impedance matching unit impedance-matching a signal summed by the signal summing unit,
• wherein the first common gate-type amplifying unit and the second common gate-type amplifying unit are formed in a cascode structure in which the first common gate-type amplifying unit and the second common gate-type amplifying unit are stacked between the source voltage terminal and a ground terminal,
• the first common gate-type amplifying unit includes:
• a first NMOS transistor amplifying the input signal and providing the first signal to the signal summing unit;
• and
• a first PMOS transistor amplifying the input signal and providing the second signal to the signal summing unit,
• the second common gate-type amplifying unit includes:
• a second NMOS transistor amplifying the input signal and providing the third signal to the signal summing unit;
• and
• a second PMOS transistor amplifying the input signal and providing the fourth signal to the signal summing unit,
• the first NMOS transistor, the first PMOS transistor, the second NMOS transistor, and the second PMOS transistor are connected to each other in series between the source voltage terminal and the ground, to form a single current path.