Amplifying circuit
AssigneeLapis Semiconductor Co., Ltd.
InventorsHiroyoshi ICHIKURA, Koji HIGUCHI
Life of this patent
Estimating the term…
Abstract
An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.
Claims14
An amplifying circuit for amplifying an input signal applied thereto through its input line, and for outputting the amplified signal through its output line, the amplifying circuit comprising:
- a first differential amplifier;
- a second differential amplifier having an input capacitance larger than the first differential amplifier;
- and
- an amplifier switch unit for outputting, through the output line, a signal caused by amplification of the input signal in the first differential amplifier in response to an amplification mode setting signal indicative of a high speed mode, and for outputting, through the output line, a signal caused by amplification of the input signal in the second differential amplifier, in response to the amplification mode setting signal indicative of a small offset mode.
An amplifying circuit for amplifying an input signal applied thereto through its input line and for outputting the amplified signal through its output line, the amplifying circuit comprising:
- a first differential pair having a first transistor and a second transistor, the first transistor being configured to pass to a first line a current corresponding to a level of a signal supplied to a gate terminal, the second transistor being configured to pass to a second line a current corresponding to a level of a signal supplied to a gate terminal;
- a second differential pair having a third transistor and a fourth transistor, the third transistor having an input capacitance larger than the first transistor and the second transistor and being configured to pass to the first line a current corresponding to a level of a signal supplied to a gate terminal, the fourth transistor having an input capacitance larger than the first transistor and the second transistor and being configured to pass to the second line a current corresponding to a level of a signal supplied to a gate terminal;
- a current source for generating a composite current of the current passing through the first line and the current passing through the second line;
- an output transistor for sending out to the output line a current corresponding to a voltage of the first line;
- and
- an amplifier switch unit for supplying the input signal to the gate terminal of the first transistor in the first differential pair while connecting the output line to the gate terminal of the second transistor in response to an amplification mode setting signal indicative of a high speed mode, and for supplying the input signal to the gate terminal of the third transistor in the second differential pair while connecting the output line to the gate terminal of the fourth transistor in response to the amplification mode setting signal indicative of a small offset mode.
Dependencies are inferred from the claim text.