Planarization layer for organic electronic devices
AssigneesMerck Patent GmbH, Promerus, LLC
InventorsPiotr Wierzchowiec, Tomas Backlund, Li W. Tan, Irina Afonina, Pawel Miskiewick, Paul C. Brookes, Larry F. Rhodes, Andrew Bell
Life of this patent
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Abstract
The invention relates to organic electronic devices containing polycycloolefin planarization layers between the substrate and a functional layer such as a semiconducting layer, dielectric layer, or electrode; to the use of polycycloolefins as a planarization layer on the substrate of an organic electronic device; and to processes for preparing such polycycloolefin planarization layers and organic electronic devices.
Claims28
An organic electronic device comprising a substrate having a planarization layer disposed directly on the substrate, and provided on said substrate a functional layer selected from semiconducting layers, dielectric layers, and electrodes, wherein the planarization layer is positioned between the substrate and the functional layer, wherein said planarization layer comprises a polycycloolefinic polymer.
A process for preparing a top gate OFET, the process comprising:
- a) depositing a layer of planarization material, which comprises a polycycloolefinic polymer on a substrate,
- b) forming source and drain electrodes on at least a portion of the planarization layer,
- c) depositing a layer of organic semiconductor material over said planarization layer and the source and drain electrodes,
- d) depositing a layer of dielectric material on the organic semiconductor layer,
- e) forming a gate electrode on at least a portion of the dielectric layer and
- f) optionally depositing a layer selected from an insulating, protection, stabilizing, and/or adhesive layer, on the gate electrode and portions of the dielectric layer.
A process for preparing a bottom gate OFET, the process comprising:
- a) depositing a layer of planarization material, which comprises a polycycloolefinic polymer on a substrate,
- b) forming a gate electrode on at least a portion of the planarization layer,
- c) depositing a layer of dielectric material over said planarization layer and the gate electrode,
- d) depositing a layer of organic semiconductor material) on dielectric layer,
- e) forming source and drain electrodes on at least a portion of organic semiconductor layers as depicted, and
- f) optionally depositing a layer selected from an insulating, protection, stabilizing, and/or adhesive layer, on the source and drain electrodes and portions of the organic semiconductor layer.
Dependencies are inferred from the claim text.