US 2016/0079436 A1Published application

Semiconductor device

AssigneeKabushiki Kaisha Toshiba

InventorsJun NISHIMURA, Nobuaki YASUTAKE, Takayuki OKAMURA

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Abstract

According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

Claims13

Dependent claims

A semiconductor device comprising:

a first line configured to extend in a first direction along a surface of a semiconductor substrate;
and
a first transistor configured to be disposed above the first line,
the first transistor including:
a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line;
a third semiconductor region which is provided, in the second direction, on an opposite side of the semiconductor substrate with respect to the first semiconductor region in the first semiconductor layer;
a second semiconductor region which is provided, in the second direction, between the first semiconductor region and the third semiconductor region in the first semiconductor layer;
a first gate insulating film which covers a first side face of the second semiconductor region;
a first gate electrode which covers the first side face of the second semiconductor region through the first gate insulating film;
a second line configured to be connected to an upper face of the first semiconductor layer and to extend in the second direction;
a plurality of third lines configured to extend along the surface of the semiconductor substrate and to intersect with the second line above the first transistor;
and
a plurality of memory cells configured to be disposed at positions where the second line and the plurality of third lines intersect,
a face of the first gate electrode which abuts on the first gate insulating film being curved so that a portion on a side of the first semiconductor region is spaced apart from the first semiconductor layer.

11 more elements

A semiconductor device comprising:

a first line configured to extend in a first direction along a surface of a semiconductor substrate;
and
a first transistor configured to be disposed above the first line,
the first transistor including:
a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line;
a third semiconductor region which is provided, in the second direction, on an opposite side of the semiconductor substrate with respect to the first semiconductor region in the first semiconductor layer;
a second semiconductor region which is provided, in the second direction, between the first semiconductor region and the third semiconductor region in the first semiconductor layer;
a first gate insulating film which covers a first side face of the second semiconductor region;
a first gate electrode which covers the first side face of the second semiconductor region through the first gate insulating film;
a second line configured to be connected to an upper face of the first semiconductor layer and to extend in the second direction;
a plurality of third lines configured to extend along the surface of the semiconductor substrate and to intersect with the second line above the first transistor;
and
a plurality of memory cells configured to be disposed at positions where the second line and the plurality of third lines intersect,
a face of the first gate electrode which abuts on the first gate insulating film being curved so that a portion on a side of the third semiconductor region is spaced apart from the first semiconductor layer.

11 more elements

A semiconductor device comprising:

a first line configured to extend in a first direction along a surface of a semiconductor substrate;
and
a first transistor configured to be disposed above the first line,
wherein the first transistor includes
a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line,
a third semiconductor region which is provided, in the second direction, on an opposite side of the semiconductor substrate with respect to the first semiconductor region in the first semiconductor layer,
a second semiconductor region which is provided, in the second direction, between the first semiconductor region and the third semiconductor region in the first semiconductor layer,
a first gate insulating film which covers a first side face of the second semiconductor region, and
a first gate electrode which covers the first side face of the second semiconductor region through the first gate insulating film, a face of the first gate electrode which abuts on the first gate insulating film being curved so that a portion on a side of the third semiconductor region is spaced apart from the first semiconductor layer.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/952,156Filed 25 Nov 2015
Priority: 6 Mar 2014
Published: 17 Mar 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 30/6706
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device: for…
H10B 63/34
Comprising selection components having three or more electrodes, e.g. transistors: of the vertical channel field-effect transistor type
H10B 63/845
Arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays: the switching components being connected to a common vertical conductor
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs

Family

Application61/949,060Us provisional application · filed 6 Mar 2014
Application14/461,720Division · filed 18 Aug 2014
Application14/952,156Division
US 2015/0255510 A1Published application
US 9,583,629 B2Related patent
US 2016/0079436 A1This patent

From the US filing history. Foreign family members aren’t listed.