US 2016/0079426 A1 · SEMICONDUCTOR DEVICE

Abstract

To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

Claims10

Dependent claims

1-9. (canceled)

Dependencies are inferred from the claim text.

Facts

Application

14/952,782Filed 25 Nov 2015

Priority

JP 2013-17599127 Aug 2013

Published

17 Mar 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/798
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being provided in or under the channel regions
H10D 30/021
Manufacture or treatment: of FETs having insulated gates [IGFET]
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/603
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having asymmetry in the channel direction, e.g. lateral…

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims10