Non-planar gate all-around device and method of fabrication thereof

A semiconductor device, comprising:

• a semiconductor substrate comprising a first material, the first material having a first lattice constant;
• a source region above the substrate, the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;
• a drain region above the substrate, the drain region comprising the second material;
• a nanowire, the nanowire being coupled to the source region and being coupled to the drain region, the nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant;
• a gate dielectric layer around at least a portion of the nanowire;
• and
• a gate electrode around at least a portion of the nanowire and, the gate electrode being separated from the nanowire by at least the gate dielectric layer.